Multistage Interconnection Network Control Seed Memory Reduction
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Solution Overview
Problem
Multistage interconnection networks like Omega networks face challenges in efficiently processing non-standard numbers of inputs and outputs, leading to unused terminals and increased control signal memory requirements, which complicates interleaving and de-interleaving operations.
Innovation Solution
Implementing a configurable (N×N) multistage interconnection network with fixed mappings for unused terminals and using a control-seed value permutated to generate control signals, reducing the number of control bits needed and allowing flexible routing without changing switch configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multistage interconnection network is designed to handle non-standard numbers of inputs and outputs, then the network can process more diverse signal processing operations, but unused terminals increase and memory requirements for control signals increase
Solution Approach 1:
The control signal generation is segmented into two parts: a compact control-seed value stored in memory and expansion logic that generates full control signals on-demand. This segmentation allows the system to handle diverse network configurations without storing large control signal tables, resolving the contradiction between adaptability and memory requirements.
Solution Approach 2:
The control-seed value acts as an intermediary between the desired network configuration and the actual control signals. Instead of directly storing and managing large control signal data structures, the system uses the compact control-seed as a mediator that can be expanded into full control signals through deterministic logic, reducing memory requirements while maintaining versatility.
2Device complexity
If control signal memory size is reduced, then device complexity and resource usage decrease, but the ability to handle various interleaving configurations is limited
Solution Approach 1:
The system dynamically generates control signals from a static control-seed value based on the required network configuration. This dynamic approach allows the same compact memory structure to support multiple interleaving configurations by changing the control-seed or expansion parameters, rather than requiring separate stored control signals for each configuration.
Solution Approach 2:
The system changes parameters of the control signal generation process (such as the control-seed value or expansion logic parameters) to adapt to different interleaving configurations. This allows a single compact memory structure to support multiple configurations by varying generation parameters rather than storing separate control signals for each configuration.
3Adaptability or versatility
If unused terminals are dynamically mapped, then routing flexibility is improved, but output terminal usage becomes inconsistent across operations
Solution Approach 1:
The system performs preliminary mapping of unused terminals to fixed output terminals before the interconnection network operates. This preliminary action ensures that regardless of how control signals are generated or configured, unused terminals consistently map to the same output terminals, providing stability and predictability while maintaining routing flexibility for used terminals.
Data Source
AI summary
In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages.