Multi-Stage Level Shifter for Low-Current Voltage Domain Crossing
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Solution Overview
Problem
Circuit arrangements face challenges in ensuring digital signals can effectively cross from one voltage domain to another without causing undesirable behavior in components operating in different supply voltage domains, due to disparities in logic high and low voltage levels.
Innovation Solution
A level shifter arrangement using diode-connected PMOS transistors and CMOS inverters is employed, with multiple stages configured to gradually shift the voltage levels of the digital signal from a first supply voltage domain to a second, higher supply voltage domain, reducing voltage drops and static current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a digital signal is directly transmitted from a first voltage domain to a second voltage domain with higher supply voltage, then the transmission is simple, but the signal voltage levels are incompatible and may cause undesirable behavior in the receiving circuit components
Solution Approach 1:
The level shifter is divided into multiple stages, where each stage gradually shifts the voltage level of the digital signal from the first voltage domain to the second voltage domain. This segmented approach ensures that the signal transitions through intermediate voltage levels, maintaining compatibility with the receiving circuit components operating at the higher supply voltage.
Solution Approach 2:
The level shifter acts as an intermediary circuit between the first voltage domain circuit and the second voltage domain circuit. It receives the digital signal from the first voltage domain, shifts its voltage levels, and provides the transformed signal to the second voltage domain circuit, ensuring proper voltage level matching and preventing undesirable behavior in the receiving components.
2Reliability
If voltage level shifting is implemented using conventional circuits, then signal compatibility is improved, but cross-currents and static current consumption increase
Solution Approach 1:
The level shifter utilizes the threshold voltage characteristics of diode-connected PMOS transistors to achieve voltage level shifting. By carefully selecting and configuring these transistors, the circuit transforms the input signal voltage levels to match the second voltage domain while minimizing current consumption. The diode-connected PMOS transistors operate in a controlled manner to reduce static current compared to conventional level shifting approaches.
3Reliability
If multiple stages of voltage shifting are used, then signal compatibility and reduced current consumption are achieved, but the circuit complexity increases
Solution Approach 1:
The level shifter is divided into multiple stages, where each stage gradually shifts the voltage level of the digital signal from the first voltage domain to the second voltage domain. This segmented approach ensures that the signal transitions through intermediate voltage levels, maintaining compatibility with the receiving circuit components operating at the higher supply voltage.
Solution Approach 2:
The level shifter acts as an intermediary circuit between the first voltage domain circuit and the second voltage domain circuit. It receives the digital signal from the first voltage domain, shifts its voltage levels, and provides the transformed signal to the second voltage domain circuit, ensuring proper voltage level matching and preventing undesirable behavior in the receiving components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the effective transmission of digital signals across voltage domains, minimizing cross-currents and static current consumption, while ensuring compatibility with logic high and low trigger levels of the receiving circuit components.
Implementation Method 1
The level shifter arrangement comprises a first stage and a second stage; wherein the first stage comprises a first arrangement of one or more diode-connected PMOS transistors
Implementation Method 2
the first and second arrangements of diode-connected PMOS transistors are configured such that that a voltage drop provided by the first arrangement is greater than the voltage drop provided by the second arrangement
Implementation Method 3
the first CMOS inverter arrangement is configured to receive the first digital output signal and provide a first intermediate digital output signal to the second CMOS inverter arrangement of the second stage
Data Source
Figure 1~2
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Figure 5~6
AI summary
An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.