Multi-Stage Level Shifter for Cross-Voltage Signal Integrity
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Solution Overview
Problem
Ensuring that digital signals can effectively cross from one voltage domain to another without causing undesirable behavior in circuit components operating in different supply voltage domains is challenging due to disparities in voltage levels, leading to potential cross-currents and operational issues.
Innovation Solution
A level shifter arrangement using diode-connected PMOS transistors and CMOS inverters is employed to incrementally shift the voltage levels of digital signals from a first voltage domain to a second, higher voltage domain, reducing voltage drops and static current consumption while maintaining logic high and low states, thereby preventing cross-currents and ensuring compatible operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a digital signal is directly transmitted from a first voltage domain to a second voltage domain with higher supply voltage, then the circuit structure remains simple, but cross-currents occur and component operation becomes unreliable
Solution Approach 1:
The level shifter is divided into multiple stages, each stage containing diode-connected PMOS transistors and CMOS inverter arrangements. This segmentation allows gradual voltage level transition from the first voltage domain to the second voltage domain, preventing direct voltage mismatch and cross-currents while maintaining operational reliability.
Solution Approach 2:
Diode-connected PMOS transistors are used as intermediary elements between the first and second voltage domains. These transistors with their gate connected to drain create a controlled path that mediates the voltage transition, allowing signal level shifting while blocking harmful cross-currents.
2Loss of energy
If voltage levels are shifted using a single-stage level shifter, then the device complexity is reduced, but voltage drops increase and static current consumption rises
Solution Approach 1:
The level shifting function is segmented into multiple stages, distributing the voltage transition across several smaller steps. Each stage handles a portion of the voltage difference, reducing the voltage drop per stage and consequently lowering static current consumption compared to a single-stage design.
Solution Approach 2:
The patent changes the operating parameters of the transistors in each stage, specifically using diode-connected PMOS transistors with gate connected to drain. This parameter change optimizes the voltage-drop characteristics and reduces static current consumption at each stage, cumulatively achieving lower overall energy loss.
3Loss of energy
If diode-connected PMOS transistors are used in the level shifter arrangement, then static current consumption is reduced, but the device complexity increases
Solution Approach 1:
The patent applies parameter changes by connecting the gate to the drain of PMOS transistors, creating diode-connected configurations. This parameter change fundamentally alters the transistor behavior to reduce static current consumption. The complexity increase is justified by the significant energy loss reduction achieved through this parameter modification.
Data Source
AI summary
An apparatus comprising a first voltage domain circuit including a first circuit component configured to provide a first digital output signal; a second voltage domain circuit comprising a second circuit component; a level shifter arrangement configured to receive the first digital output signal and generate a second digital output signal based thereon with an increased voltage level of the high state, and provide said second digital output signal to the second circuit component; wherein the level shifter arrangement comprises at least one stage, the at least one stage comprising an arrangement of one or more diode-connected PMOS transistors, coupled to a CMOS inverter arrangement; the CMOS inverter arrangement of a first of the at least one stages configured to receive the first digital output signal and the CMOS inverter arrangement of a final stage of the at least one stages configured to output said second digital output signal.