Multistage Network Tile Array for Low-Latency On-Chip Routing
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Solution Overview
Problem
Existing multistage networks for connecting processor tiles on a chip face challenges in efficiently routing network traffic due to reliance on rectangular topologies and multiple switching layers, which can lead to increased latency and complexity in layout and fault tolerance.
Innovation Solution
Implementing a multistage network using a two-dimensional array of tiles with direct logical connections between switches through proximity communication and passthroughs, allowing for 'all-to-all' connectivity within rows and columns, and utilizing logical bricks corresponding to multiple layers to route traffic efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple switching layers are used to connect processor tiles, then fault tolerance and reliability are improved, but switching delays and network latency increase
Solution Approach 1:
The network is divided into multiple functional layers (top layer for ingress, bottom layer for egress, intermediate layers for routing) with each layer performing specific switching functions. This segmentation allows traffic to be processed in parallel across layers, reducing overall latency while maintaining fault tolerance through redundant paths.
Solution Approach 2:
Intermediate bricks serve as mediator components between the top and bottom switching layers. These intermediate bricks provide additional routing capacity and redundancy without requiring traffic to pass through multiple complete switching stages, thereby reducing switching delays while maintaining reliability.
2Ease of manufacture
If traditional rectangular topology is used for on-chip networks, then layout simplicity is maintained, but connectivity efficiency and routing flexibility are limited
Solution Approach 1:
The network architecture transitions from a traditional two-dimensional rectangular topology to a three-dimensional layered structure. By adding the vertical dimension with multiple switching layers (top, intermediate, bottom), the system achieves enhanced routing flexibility and connectivity while maintaining the simple rectangular footprint for layout ease.
Solution Approach 2:
Each tile in the array is designed with universal multi-functionality, containing both top and bottom bricks that can operate as switching elements or passthroughs depending on routing needs. This allows the same physical structure to serve multiple routing functions, enhancing adaptability without complicating the layout.
3Productivity
If direct logical connections are implemented between non-adjacent tiles, then routing efficiency is improved, but physical layout complexity increases
Solution Approach 1:
The patent uses logical copying of connection patterns across multiple layers. Instead of creating unique physical connections for each non-adjacent tile pair, the same logical connection pattern is replicated across top, intermediate, and bottom layers, achieving efficient routing while reusing physical infrastructure.
Solution Approach 2:
The network architecture implements a nested structure where intermediate bricks are embedded within the layered framework, and logical connections are nested across multiple switching layers. This nesting allows direct logical connections between non-adjacent tiles to be achieved by routing through intermediate layers without adding proportional physical complexity.
Data Source
AI summary
A network, including: a first tile having a processor, a top brick connected to the processor, a first bottom brick, and a first intermediate brick; a second tile having a second intermediate brick and a second bottom brick; multiple connections connecting the top brick with the second intermediate brick and the first intermediate brick with the second bottom brick using a passthrough on an intermediate tile between the first and second tiles, where the first, intermediate, and second tiles are positioned in a row; and a third tile having a plurality of caches connected to a third bottom brick, where the second and third tiles are positioned in a column, and the first bottom brick, second bottom brick, and third bottom brick belong to a bottom layer of the network, and where the first and second intermediate bricks belong to an intermediate layer of the network.