Multi-Stage Resistor DAC Architecture for Precision and Low Glitch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current digital-to-analog converters (DACs) face limitations in terms of power consumption, speed, glitch magnitude, and area requirements, particularly in achieving precise analog output voltage representations from digital inputs, especially when dealing with large binary values.
Innovation Solution
A digital-to-analog converter system comprising multiple stages, including a most significant bits (MSB) stage, intermediate significant bits (ISB) stage, and least significant bits (LSB) stage, utilizing switched resistor networks and Gray code conversion to efficiently generate analog outputs, with each stage contributing to the overall precision and reducing resistance values needed for conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional single-stage DAC architecture is used, then device complexity is low, but manufacturing precision and analog output precision are insufficient
Solution Approach 1:
The DAC is divided into multiple stages: a first DAC stage that processes MSBs and generates a first analog output, and a second DAC stage that processes LSBs and generates a second analog output. The analog output is obtained by combining these two outputs. This segmentation allows each stage to be optimized independently, improving overall precision while managing complexity through modular design.
2Manufacturing precision
If large resistance values are used in DAC, then power consumption is reduced, but analog output precision and voltage representation capability deteriorate
Solution Approach 1:
By dividing the DAC into two stages with different resistance configurations, the system can use smaller resistance values in the second stage (processing LSBs) without compromising overall precision. The first stage handles MSBs with one resistance configuration, and the second stage handles LSBs with a different resistance configuration, enabling better voltage representation with reduced resistance values and associated power consumption benefits.
Solution Approach 2:
Different resistance values and configurations are used in different stages of the DAC. The first DAC stage uses a first set of resistance values optimized for MSB processing, while the second DAC stage uses a second set of resistance values optimized for LSB processing. This local optimization allows each stage to operate with resistance values suited to its specific function, improving overall precision while managing power consumption.
3Speed
If switching speed is increased in DAC, then conversion speed is improved, but switching-induced power consumption and glitch magnitude increase
Solution Approach 1:
The conversion process is segmented into two stages that operate with different switching characteristics. The first stage processes MSBs with switching optimized for higher significance bits, while the second stage processes LSBs with switching optimized for lower significance bits. This allows the system to achieve high conversion speed without excessive switching power consumption, as each stage's switching activity is tailored to its specific bit significance.
Data Source
AI summary
A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.