Multistage Round Robin Arbitration for Low Latency
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Solution Overview
Problem
Conventional round robin arbitration schemes suffer from high latency and reduced clock frequency as the number of request signals and queues increase, limiting system performance.
Innovation Solution
A multistage round robin arbitration architecture is proposed, comprising a first and second stage round robin arbitration, utilizing logical gates, multiplexers, and a delay element to improve performance by pipelining and reducing latency, allowing for increased operating clock frequency and efficient access to common resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If scanning arbiters are used to facilitate access grants as quickly as possible, then access speed is improved, but latency increases as the number of request signals increases
Solution Approach 1:
The arbitration process is divided into multiple stages: a first stage round robin arbitration that receives request signals and selects a subset, and a second stage round robin arbitration that grants access to the selected subset. This segmentation allows the system to handle large numbers of request signals efficiently while maintaining low latency, as each stage processes a manageable portion of the total requests.
2Loss of time
If the window size is increased to reduce latency, then latency is reduced, but clock frequency decreases
Solution Approach 1:
By segmenting the arbitration into two stages with different window sizes, the system can use a smaller effective window size in each stage while maintaining low overall latency. The first stage processes a subset of requests with a smaller window, and the second stage processes another subset, allowing the system to achieve low latency without requiring a large window size that would reduce clock frequency.
Solution Approach 2:
The multistage architecture dynamically adjusts the processing window size at each stage, allowing the system to optimize for both latency and clock frequency. The first stage arbitration processes requests with one window size configuration, and the second stage processes with another configuration, enabling dynamic optimization that maintains high clock frequency while achieving low latency.
3Productivity
If high numbers of queues and larger queue size are used to improve system performance, then system performance is improved, but latency increases
Solution Approach 1:
The system segments the large number of queues into multiple groups that are processed in different stages of arbitration. The first stage round robin arbitration handles a subset of queue groups, and the second stage handles another subset, allowing the system to support high numbers of queues and large queue sizes while maintaining low latency through distributed processing across stages.
Data Source
AI summary
A device includes a first and a second stage round robin arbitrations. The first stage receives request signals and selects a subset the request signals. Each request signal is associated with whether a component is requesting access to a common resource. The second stage receives the selected subset and grants access to the common resource to each request signal of the selected subset that is requesting access, in a round robin fashion. The second stage outputs an enable signal to the first stage when the selected subset is processed. The first stage selects another subset and transmits the selected another subset to the second stage for round robin processing thereof. The process is repeated until all subsets with at least one request signal to access the common resource is processed and granted access in a round robin fashion.