Multi-Stage Serializer Circuit With Phase-Shifted Clocks for Low Latency
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Solution Overview
Problem
Existing serializer circuits face challenges in reducing latency and ensuring sufficient critical path for high-speed data signal serialization due to delays introduced by flip-flops and multiplexers, which results in incorrect data output and increased latency.
Innovation Solution
The proposed system employs a serializer circuit architecture with intermediate serializer circuits, a tri-state circuit, and output serializer circuits that utilize phase-differed clock signals to serialize input data signals, ensuring a critical path equal to a full clock cycle, thereby reducing latency and ensuring accurate high-speed data serialization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a 2:1 serializer circuit with multiplexer and latch is used to serialize two input data signals, then the input data signals are serialized, but the second input data signal is delayed by half cycle of the clock signal introducing latency
Solution Approach 1:
The patent divides the serialization process into multiple stages using intermediate serializer circuits. Each intermediate serializer handles a subset of input signals and outputs intermediate serialized signals, which are then further serialized by output serializers. This segmentation reduces the latency in each stage compared to a single large serializer.
Solution Approach 2:
The patent introduces intermediate serializer circuits as intermediary components between the parallel input signals and the final serialized output. These intermediate serializers convert parallel inputs to intermediate serialized signals, which are then processed by output serializers to produce the final serialized output, thereby reducing overall latency.
2Speed
If flip-flops are placed in close proximity to the multiplexer to reduce time interval, then the physical path is reduced, but latency is introduced by the flip-flops
Solution Approach 1:
The patent segments the serialization function across multiple specialized circuits (intermediate serializers and output serializers) rather than using a single circuit with flip-flops near the multiplexer. This segmentation allows each stage to be optimized for its specific function, reducing overall latency without introducing excessive flip-flop delays.
Solution Approach 2:
The patent maintains continuous data flow through the intermediate serializers and output serializers with proper clocking and timing control. The intermediate serialized signals are continuously passed through the system without unnecessary stopping or latching, ensuring continuous useful action and minimizing latency.
3Speed
If the critical path is set to half cycle of the clock signal, then the serializer circuit operates at high speed, but high speed input data signals cannot be properly serialized
Solution Approach 1:
The patent divides the critical path into multiple smaller critical paths across intermediate and output serializer stages. Each stage operates with its own timing requirements, allowing the overall system to handle high-speed signals reliably by breaking down the timing constraints into manageable segments.
Solution Approach 2:
The patent adds temporal dimension to the serialization process by using multiple clock phases and staged processing. Instead of a single critical path operating at half clock cycle, the system uses multiple stages with different timing, effectively increasing the time dimension available for reliable high-speed serialization.
Data Source
AI summary
A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.