Multistage Shadow Tag Memory Probe Comparison

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Solution Overview

Problem

The communication of coherency probes between caches in processing systems negatively impacts performance and power consumption due to the need for extensive comparisons in cache hierarchies.

Innovation Solution

Implementing a multistage shadow tag memory that compares probe tags in multiple stages, reducing the number of necessary comparisons by predicting potential matches using subsets of the probe tag bits, thereby conserving power and resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If extensive comparisons are performed for each probe tag in cache hierarchies, then memory coherency is ensured, but power consumption and processing time increase

Engineering Contradiction:
Improvememory coherencyVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The probe tag is divided into multiple segments, and the comparison process is segmented into multiple stages. In each stage, only a subset of tag bits is compared, reducing the computational burden in each individual stage while maintaining overall comparison accuracy for ensuring memory coherency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary comparisons using subsets of probe tag bits before completing the full tag comparison. This preliminary action identifies potential matches early in the process, allowing the system to focus subsequent comparison resources only on promising candidates rather than exhaustively comparing all tags.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If extensive comparisons are performed for each probe tag in cache hierarchies, then memory coherency is ensured, but processing speed decreases

Engineering Contradiction:
Improvememory coherencyVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The comparison operation is segmented into multiple stages, each handling a portion of the tag bits. This segmentation enables parallel processing of different tag comparisons simultaneously, as not all tags need to be fully compared sequentially, thereby improving processing throughput while maintaining coherency verification.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Preliminary comparisons using subset bits are performed to quickly eliminate non-matching tags before completing full tag comparisons. This filtering action reduces the number of full comparisons needed, accelerating the overall probe resolution process while still ensuring accurate coherency determination.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If full probe tag comparisons are performed for all cache entries, then accurate match identification is achieved, but the number of comparisons required increases

Engineering Contradiction:
Improvematch identification accuracyVSAvoidcomparisons per unit time
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The system performs preliminary comparisons using subsets of probe tag bits to identify potential matches before conducting full tag comparisons. This two-stage approach maintains accurate match identification by verifying complete tag matches for only those entries that pass the preliminary filter, significantly reducing the total number of full comparisons required.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The tag comparison is segmented into preliminary subset-bit comparisons and subsequent full-tag comparisons. This segmentation allows the system to process multiple cache entries in parallel during the preliminary stage, improving productivity while preserving measurement precision through follow-up complete comparisons for candidate matches.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9916246B1Predictive multistage comparison for associative memory
Publication Date: 2018.03.13 ADVANCED MICRO DEVICES INC
  • US9916246B1 patent drawing
  • US9916246B1 patent drawing
  • US9916246B1 patent drawing

AI summary

A processing system includes a shadow tag memory, which stores a plurality of entries containing coherency information for the cachelines residing at the various levels of private caches. If a cache miss occurs at a private cache, or if coherency information for a cacheline requires updating, a probe is sent to the shadow tag memory maintained at the shared cache to determine whether the requested (or affected) cacheline is stored at another private cache. The probe includes a tag which can be divided into two or more portions. To more efficiently compare the probe tag to the shadow tag entries, the comparison is performed in multiple stages based on the portions of the probe tag.