Multi-Stage Resettable Sigma-Delta ADC for Fewer Samples
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Solution Overview
Problem
Single loop sigma-delta analog-to-digital converters face limitations in achieving high resolution with low sample counts, leading to potential overload and requiring complex circuitry to manage noise transfer functions.
Innovation Solution
A resettable multi-stage sigma-delta A/D converter is developed, featuring a cascade of at least two resettable sigma-delta loops with a digital decimation filter, where the number and allocation of integrators in the decimation filter match those in the sigma-delta loops, and a reset line is used to conserve energy by turning off active components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single loop sigma-delta converter uses more integrators to achieve higher resolution, then measurement precision improves, but device complexity increases and signal overload occurs
Solution Approach 1:
The patent divides the single loop sigma-delta converter into multiple cascaded loops, each with its own integrators. The first loop has a first set of integrators and the second loop has a second set of integrators. This segmentation allows the system to achieve high resolution through multiple stages of integration rather than requiring a single complex loop, thereby improving measurement precision while managing device complexity through modular architecture.
2Productivity
If a single loop sigma-delta converter increases the number of integrators to reduce sample count, then productivity improves, but signal levels exceed acceptable levels causing overload
Solution Approach 1:
By segmenting the integrators into multiple loops, each loop processes a portion of the integration function. This prevents any single integrator stage from accumulating excessive signal levels that would cause overload, while still achieving the desired reduction in sample count through the combined effect of multiple integration stages across the cascaded loops.
Solution Approach 2:
The patent introduces a temporal dimension by cascading multiple loops in sequence, where the output of one loop becomes the input to the next. This multi-stage temporal processing allows the system to achieve high conversion speed without requiring all integrators to operate simultaneously at high signal levels, thereby avoiding overload while maintaining productivity.
3Measurement precision
If continuous operation of active components is maintained, then measurement precision improves, but energy consumption increases
Solution Approach 1:
The patent implements periodic resetting of the integrators through a reset signal that is applied to both loops. This periodic action allows the active components to be turned off between reset cycles to conserve energy, while still maintaining measurement precision by ensuring the integrators are properly initialized and stabilized at regular intervals. The cascaded loop structure allows for coordinated resetting that maintains output stability.
Data Source
AI summary
A resettable multi-stage sigma-delta analog-to-digital (A/D) converter enables a sampled analog signal to be resolve with fewer cycles than a resettable single sigma-delta A/D converter. The resettable multi-stage converter includes a cascade of at least two resettable sigma-delta loops having a total number of integrators and an allocation of delays, a digital decimation filter, the digital decimation filter being coupled to the at least two resettable sigma-delta loops and the digital decimation filter includes a cascade of integrators, a number of the integrators in the cascade of integrators for the decimation filter being equal to the total number of integrators in the cascade of at least two resettable sigma-delta loops and an allocation of delays in the cascade of integrators being equal to the allocation of delays in the cascade of at least two resettable sigma-delta loops, a plurality of A/D converters having a resolution that is less than a resolution of the resettable multi-stage sigma-delta A/D converter, a plurality of digital-to-analog (D/A) converters, the plurality of A/D converters and the plurality of D/A converters coupling the cascade of at least two resettable sigma-delta loops to the digital decimation filter, and a reset line coupled to the integrators in the cascade of integrators for the at least two resettable sigma-delta loops and coupled to the integrators in the cascade of integrators for the digital decimation filter.