Multi-Stage TDC Digital Locking Loop for Fast Phase Locking
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Solution Overview
Problem
Digital phase-locked loops (DPLLs) require long locking times due to the need for wide time-to-digital converters (TDCs) with high area and power consumption, which is a challenge for applications requiring fast locking times.
Innovation Solution
A digital locking loop circuit with a multi-stage time-to-digital converter that includes phase-error detection stages operating at different resolutions, combined using combinatorial logic to provide a high-resolution quantized phase error signal, allowing for faster locking times by adjusting the digitally-controlled frequency generator.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a wide time-to-digital converter (TDC) is used to provide high-resolution phase error detection, then locking time is reduced, but area and power consumption increase substantially
Solution Approach 1:
The TDC is divided into multiple stages, each detecting phase error at a different resolution. The first stage detects phase error at integer multiples of the output signal time period, the second stage detects at coarse fractions, and the third stage detects at fine fractions. This segmentation allows the system to achieve high overall resolution without requiring a single wide TDC, thereby reducing area and power consumption while maintaining fast locking times.
2Loss of time
If a wide time-to-digital converter (TDC) is used to provide high-resolution phase error detection, then locking time is reduced, but power consumption increases substantially
Solution Approach 1:
The TDC is divided into multiple stages, each detecting phase error at a different resolution. The first stage detects phase error at integer multiples of the output signal time period, the second stage detects at coarse fractions, and the third stage detects at fine fractions. This segmentation allows the system to achieve high overall resolution without requiring a single wide TDC, thereby reducing area and power consumption while maintaining fast locking times.
3Area of stationary object
If a simple phase-error detector is used, then area and power are reduced, but locking time increases
Solution Approach 1:
The TDC is divided into multiple stages, each detecting phase error at a different resolution. The first stage detects phase error at integer multiples of the output signal time period, the second stage detects at coarse fractions, and the third stage detects at fine fractions. This segmentation allows the system to achieve high overall resolution without requiring a single wide TDC, thereby reducing area and power consumption while maintaining fast locking times.
Data Source
AI summary
A digital locking loop circuit (DLLC), such as a digital phase-locked loop or digital delay-locked loop, includes a digitally-controlled frequency generator, a digital loop filter configured to output a digital control signal for the frequency generator, and a multi-stage time-to-digital converter to detect phase error between an input reference clock signal and an output signal fed back from the frequency generator, to adjust the digitally-controlled frequency generator to decrease the phase error. Each phase-error detection stage detects a phase error component at a respective resolution, and combinatorial logic combines the components into a phase error signal. The plurality of stages may operate in parallel to provide different portions of the phase error signal. The DLLC may include a fractional phase interpolator to adjust the target frequency by a fractional amount, and one of the stages includes conversion circuitry to compensate for a fractional phase. A method also is provided.