Multi-Stage Test Circuit for Faster Electromigration Testing
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Solution Overview
Problem
Conventional electro-migration tests in semiconductor devices face inefficiencies due to high test currents potentially damaging the metal and low currents requiring long test times, leading to unreasonable predictions and prolonged testing of individual metal wires.
Innovation Solution
A test circuit with multiple stages of test units connected in series, where each stage is tested at the same voltage, allowing automatic sequential testing after the previous stage fails, significantly reducing overall test time by enabling multiple electro-migration tests to be conducted simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If high test current is used to shorten test time, then test time is reduced, but the metal may be burned and lifetime prediction becomes unreasonable
Solution Approach 1:
The patent divides the test structure into multiple stages (first stage, second stage, etc.), each containing multiple test units with electro-migration test elements. This segmentation allows the system to perform multiple tests simultaneously at different locations, thereby reducing overall test time without requiring excessively high current that would damage the metal.
Solution Approach 2:
The patent combines multiple electro-migration test elements across different stages and test units into a single integrated test circuit. By applying a constant current to the power wire that feeds multiple stages, the system simultaneously tests multiple elements, achieving parallel testing that reduces total test time while maintaining safe current levels for each individual element.
2Reliability
If low test current is used to avoid metal damage, then metal safety is improved, but test time becomes excessively long
Solution Approach 1:
The test circuit is segmented into multiple independent stages that can operate simultaneously. Each stage contains test units with electro-migration test elements that are fed by the power wire. This segmentation enables parallel testing, where multiple elements are tested at the same time using safe current levels, thereby reducing total test time without compromising metal safety.
Solution Approach 2:
The patent implements a cascaded stage structure where the power wire continuously feeds current through multiple stages in sequence. When one stage completes its test, the system seamlessly continues testing other stages without interruption. This continuous operation maximizes the utilization of the test circuit and eliminates idle time, achieving efficient testing with safe current levels.
3Measurement precision
If individual electro-migration test elements are tested one by one, then test accuracy is maintained, but test time increases and efficiency decreases
Solution Approach 1:
The patent segments the test circuit into multiple independent stages, each containing multiple test units with electro-migration test elements. Each stage can be independently controlled and tested, maintaining test accuracy for each individual element while enabling parallel operation across stages. This segmentation allows simultaneous testing of multiple elements without compromising measurement precision.
Solution Approach 2:
The power wire serves a universal function by feeding current to multiple stages and test units simultaneously. The constant current source provides a common reference current that is distributed throughout the entire test circuit, enabling multiple electro-migration tests to be performed in parallel with consistent and accurate current control across all test elements.
Data Source
AI summary
The present application relates to a test circuit, comprising: M stages of test units, first terminals of test units in each stage being all connected to a power wire, second terminals of test units in each stage being all connected to a ground wire, third terminals of test units in the first stage being connected to the power wire, and third terminals of test units in the ith stage being connected to fourth terminals of test units in the (i−1)th stage; wherein, the M and i are positive integers greater than or equal to 2.