Multi-Staged Hardware Pipeline Generation from High Level Language
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Solution Overview
Problem
Existing methods for developing integrated circuits struggle to efficiently create multi-staged hardware implementations from high-level language programs, as they often require explicit designer input and are limited by single-process architectures or conservative data processing schedules, which restrict concurrent processing of data sets.
Innovation Solution
A method is introduced to generate a language-independent model from a high-level language program, identifying processing stages and stall points, and using stall release signals for reverse flow control, allowing for the creation of a multi-staged hardware implementation that can process multiple data sets concurrently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single process architecture is used to map HLL representation onto hardware description, then the hardware implementation is simpler to implement, but only a single data set can be processed at any given time
Solution Approach 1:
The invention segments the processing architecture into multiple independent processing stages (first processing stage, second processing stage, etc.), each capable of handling different data sets simultaneously. This segmentation allows the system to process multiple data sets in parallel while maintaining manageable complexity in each individual stage.
Solution Approach 2:
The invention transitions from a single-dimensional sequential processing model to a multi-dimensional parallel processing model by introducing multiple processing stages that operate simultaneously. This dimensional expansion enables concurrent processing of multiple data sets without proportionally increasing overall system complexity.
2Productivity
If pre-defined constructs are explicitly included in the HLL program to create multi-staged hardware implementations, then multiple data sets can be processed concurrently, but the designer must explicitly define each processing stage
Solution Approach 1:
The invention enables the compilation tool to automatically generate multi-staged hardware implementations from standard HLL programs without requiring designers to explicitly define processing stages. The tool self-services by analyzing the HLL code and autonomously creating the appropriate hardware description with multiple processing stages, thereby maintaining ease of use while enabling concurrent processing.
Solution Approach 2:
The invention introduces an intermediate representation layer between the HLL program and the hardware description. This intermediary representation captures the data processing logic in a form that can be automatically transformed into multi-staged hardware architecture, eliminating the need for designers to manually define processing stages while preserving the ability to process multiple data sets concurrently.
3Productivity
If multiple statically scheduled wavefronts are used to allow new data sets to be introduced prior to complete processing of previous data sets, then processing efficiency is improved, but the hardware implementation cannot dynamically adjust to process data sets earlier than the conservative N clock cycle limitation
Solution Approach 1:
The invention introduces dynamic control mechanisms that allow the hardware implementation to adaptively adjust processing timing based on actual data availability and processing status. Unlike static scheduling with fixed N-clock-cycle delays, the dynamic approach enables the system to process data sets as soon as they are ready, improving both efficiency and adaptability by responding to real-time conditions rather than predetermined schedules.
Solution Approach 2:
The invention implements feedback mechanisms that monitor the processing status of data sets and use this information to dynamically control when new data sets are introduced. This feedback-driven approach allows the system to optimize processing timing by introducing new data sets immediately when previous data sets complete processing, rather than waiting for conservative predetermined intervals, thereby achieving both high efficiency and dynamic adaptability.
Data Source
AI summary
A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.