Multi-State Logic Gates for Higher Bandwidth Computing
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Solution Overview
Problem
Current electronic logic systems are limited by their reliance on binary logic states, which restricts their computational capabilities and efficiency as they approach technological barriers such as increased power dissipation and interconnect area requirements, making it difficult to enhance computing power without increasing the number of transistors or wires.
Innovation Solution
The development of electronic logic gates that operate with more than two logic states, utilizing a truth table to perform logic operations and incorporating a selector input to perform multiple logic functions, along with binary to N logic level encoders and decoders, allowing for higher communication bandwidth without increasing the number of traces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more transistors are added to increase computing power, then computational capabilities improve, but chip area and interconnect requirements increase excessively
Solution Approach 1:
The patent combines multiple binary logic functions (AND, OR, NOT, XOR, NAND, NOR) into a single multi-state logic gate that operates with N logic states where N > 2. This merging of multiple functions into one device reduces the total number of transistors and interconnects needed, directly addressing the chip area problem while maintaining computing power.
Solution Approach 2:
The multi-state logic gate is designed to perform multiple logic functions simultaneously by utilizing N logic states instead of binary states. The gate can be configured to implement different Boolean functions through selective activation of its N-state operation, making it a universal logic element that replaces multiple specialized binary gates.
2Productivity
If the number of logic states is increased beyond binary, then functional density and communication bandwidth increase, but device complexity increases
Solution Approach 1:
The patent changes the fundamental parameter of logic states from binary (2 states) to multi-state (N states where N > 2). This parameter change enables the logic gate to process more information per operation, increasing communication bandwidth and functional density. The complexity increase is managed by using systematic encoding and decoding schemes that leverage the additional states efficiently.
3Productivity
If more gates are allocated to specific tasks to exploit concurrency, then computing bandwidth increases, but the portion of chip area devoted to interconnects becomes excessive
Solution Approach 1:
By merging multiple logic functions into single multi-state gates, the patent reduces the total number of gates required to achieve a given computing bandwidth. This reduction directly decreases the interconnect area needed, as fewer gates mean fewer connections between them, thus resolving the interconnect area problem while maintaining concurrency capabilities.
Data Source
AI summary
Electronic logic gates that operate using N logic state levels, where N is greater than 2, and methods of operating such gates. The electronic logic gates operate according to truth tables. At least two input signals each having a logic state that can range over more than two logic states are provided to the logic gates. The logic gates each provide an output signal that can have one of N logic states. Examples of gates described include NAND/NAND gates having two inputs A and B and NAND/NAND gates having three inputs A, B, and C, where A, B and C can take any of four logic states. Systems using such gates are described, and their operation illustrated. Optical logic gates that operate using N logic state levels are also described.