Multi-State ReRAM via Segmented Resistive Layers

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Solution Overview

Problem

Conventional ReRAMs are limited to switching between only two states, restricting their applications due to their binary nature.

Innovation Solution

A memory device with a substrate having conductivity regions and resistive units, where a resistance adjusting element is strategically placed between the resistive units and conductivity regions, allowing for the creation of multiple resistance states by varying the voltage applied to different voltage lines, enabling the device to switch between four distinct states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional ReRAM structure with a single resistive layer is used, then the device can be manufactured with simple process complexity, but the device is limited to switching between only two states (binary states)

Engineering Contradiction:
Improvenumber of statesVSAvoiddevice structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The single resistive layer is segmented into multiple resistive layers (first resistive layer and second resistive layer), each capable of independent resistance switching. This segmentation allows the device to achieve multiple resistance states (more than binary) while maintaining a relatively simple overall structure that can be integrated into existing semiconductor manufacturing processes

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If multiple resistive layers are added to enable multi-state switching, then the device can switch between four states, but the process complexity increases

Engineering Contradiction:
Improvenumber of statesVSAvoidprocess complexity
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

Multiple resistive layers are merged within a single memory device structure, sharing common electrodes and integration pathways. This combining approach enables multi-state switching functionality while consolidating the manufacturing process, allowing both layers to be formed and integrated using standardized semiconductor fabrication techniques rather than requiring separate device fabrication for each layer

Inventive Principle:
Principle #5Merging (Combining)

3Reliability

If a resistive layer is made conductive through dielectric breakdown, then the device achieves low resistance state, but the process requires application of sufficiently high voltage difference

Engineering Contradiction:
Improveresistance switchingVSAvoidvoltage requirement
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The resistance switching mechanism utilizes changes in material parameters through controlled dielectric breakdown. By applying sufficiently high voltage difference, the resistive layer transitions from insulating to conductive state, forming a conducting filament. This parameter change approach ensures reliable resistance switching while the multi-layer structure allows for distributed voltage application, potentially reducing the peak voltage requirement compared to single-layer designs

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the memory device to switch between four states (LL(00), LH(01), HL(10), and HH(11)), expanding its application potential beyond binary limitations while maintaining manufacturing simplicity and cost-effectiveness.

Implementation Method 1

upon application of a sufficiently high voltage difference between the top and bottom electrodes, a dielectric breakdown event can occur and this can in turn form a conducting filament between the top and bottom electrodes

Methodology Applied
Scientific EffectDielectric breakdown: Avalanche Breakdown

Data Source

PatentUS11205478B2Memory device and a method for forming the memory device
Publication Date: 2021.12.21 GLOBALFOUNDRIES SINGAPORE PTE LTD
  • US11205478B2 patent drawing
  • US11205478B2 patent drawing
  • US11205478B2 patent drawing

AI summary

A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. Second, third, and fourth voltage lines may each be electrically coupled to a conductivity region. Resistive units may be arranged between the third voltage line and the conductivity region electrically coupled to the third voltage line, and between the fourth voltage line and the conductivity region electrically coupled to the fourth voltage line. A resistance adjusting element may have at least a portion arranged between one of the resistive units and one of the conductivity regions. An amount of the resistance adjusting element between the first resistive unit and the conductivity region electrically coupled to the third voltage line may be different from that between the second resistive unit and the conductivity region electrically coupled to the fourth voltage line.