Multistory Electronic Device Testing Apparatus Vertical Stacking

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing semiconductor chip testing machines have limited efficiency due to difficulties in synchronizing transfer and testing operations, large footprint, low space utilization, and the inability to test multiple types of chips, leading to inefficiencies and downtime.

Innovation Solution

A multistory electronic device testing apparatus with a three-dimensional arrangement of feeding, binning, and testing devices, featuring a multi-axis transfer system and modular design that allows for flexible configuration and increased capacity to accommodate various types of electronic devices, reducing downtime and improving testing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a planar arrangement is used for chip testing, then the machine structure is simple, but the footprint is large and space utilization is low

Engineering Contradiction:
Improvemachine structureVSAvoidfootprint
Core Design Contradiction:
Device complexityVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar (2D) arrangement to a three-dimensional (3D) multistory arrangement. The chip testing system is organized into multiple stories vertically, with each story containing complete functional modules (feeding, testing, binning). This vertical stacking dramatically reduces the horizontal footprint while maintaining all necessary testing functions, directly resolving the contradiction between structural simplicity and space utilization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If the chip-loading/unloading zone includes a limited number of cassettes, then the machine structure is simple, but the apparatus must be temporarily shut down for cassette replacement

Engineering Contradiction:
Improvecassette systemVSAvoidtesting efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements a preliminary action by pre-loading multiple trays of chips into each cassette before testing begins. Each cassette can accommodate multiple trays (e.g., 10 trays per cassette), allowing the system to operate continuously without frequent cassette replacements. This preliminary preparation eliminates downtime and maintains high productivity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies nesting by placing multiple trays inside each cassette. The trays are nested within the cassette structure, allowing a single cassette to hold multiple trays of chips. This nested arrangement increases the capacity of each cassette, reducing the frequency of cassette replacements and maintaining continuous operation.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Device complexity

If a single machine is dedicated to one type of chip, then the testing system is simple, but the machine cannot test various types of chips

Engineering Contradiction:
Improvetesting systemVSAvoidchip type flexibility
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent implements universality by designing each story's feeding and binning device to handle multiple types of electronic devices. The system can be configured to test different chip types (e.g., mobile phone chips, computer chips, automotive chips) by adjusting the testing parameters and tray configurations. This multi-functional design allows a single machine to serve multiple testing purposes, increasing versatility without proportionally increasing complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Measurement precision

If precisely matching transfer and testing operation times is attempted, then the testing accuracy is improved, but the waiting time of transfer device or testing modules increases

Engineering Contradiction:
Improvesynchronization accuracyVSAvoidwaiting time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent achieves continuity of useful action by organizing complete testing modules (feeding, testing, binning) in each story that operate independently and continuously. The multistory architecture allows multiple testing operations to proceed simultaneously at different vertical levels, eliminating idle waiting time. Each story maintains continuous operation, and the overall system achieves high throughput without synchronization bottlenecks.

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS11740283B2Multistory electronic device testing apparatus
Publication Date: 2023.08.29 CHROMA ATE INC
  • US11740283B2 patent drawing
  • US11740283B2 patent drawing
  • US11740283B2 patent drawing

AI summary

The present invention relates to a multistory electronic device testing apparatus, which mainly comprises a feeding and binning device, a multi-axis transfer device, a chip-testing device and a main controller. The feeding and binning device includes an upper module and a lower module. The chip-testing device includes a plurality of testing units arranged vertically. The main controller not only controls the feeding, binning and testing operations, but also controls the multi-axis transfer device to transfer an electronic device to be tested or a tested electronic device between the feeding and binning device and the chip-testing device. Accordingly, the three-dimensional arrangement of the feeding and binning module and the testing device is realized, and the accommodating capacity and the testing capacity for the electronic devices to be tested and the tested electronic devices can be increased.