Multi-Tap DFFE Equalizer for Low-Noise SerDes CDR Locking
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Solution Overview
Problem
Traditional SerDes receiver architectures face challenges with coupling issues between Clock Data Recovery (CDR) and equalization adaptation, leading to sub-optimal CDR locking points and increased sensitivity to noise and crosstalk.
Innovation Solution
The proposed SerDes receiver architecture integrates a Decision Feedforward Equalizer (DFFE) with joint auto-adaptation, allowing for optimal shaping of the signal for improved CDR and SerDes performance. This architecture decouples CDR and equalization adaptation by tapping the CDR from an intermediate node in the equalization data path, ensuring a symmetric pulse response optimal for Mueller-Muller CDR.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional SerDes receiver architecture is used with separate CDR and equalization adaptation, then the system is simpler to implement, but the CDR locking point becomes sub-optimal and the system becomes more sensitive to noise and crosstalk
Solution Approach 1:
The equalization data path is segmented into multiple stages: an intermediate node that feeds CDR and a final node that provides the equalized output. This segmentation allows CDR to lock to an intermediate signal with optimal characteristics while still achieving full equalization at the final output, resolving the contradiction between CDR performance and system complexity.
Solution Approach 2:
An intermediate equalization node is introduced as a mediator between the input signal and the CDR block. This intermediate node provides a signal with optimized pulse characteristics that enables optimal CDR locking, while the complete equalization is achieved through subsequent processing stages.
2Reliability
If FFE is used for both precursor and postcursor ISI correction, then both types of ISI are corrected, but noise and crosstalk are amplified
Solution Approach 1:
The equalization function is segmented between FFE and DFFE blocks. The FFE handles initial equalization while the DFFE provides additional equalization stages with decision-directed operation. This segmentation allows ISI correction without the noise amplification problems of pure FFE, as the decision-directed approach uses detected symbols to guide the equalization process.
Solution Approach 2:
The DFFE block implements decision-directed equalization where detected data symbols are fed back to control the equalization process. This feedback mechanism allows the system to correct ISI adaptively without amplifying noise and crosstalk, as the equalization is guided by actual detected decisions rather than purely adaptive coefficient adjustment.
3Object-affected harmful factors
If DFE is used for postcursor ISI correction, then noise is not amplified, but the ability to correct precursor ISI is lost
Solution Approach 1:
The system merges FFE and DFFE blocks to create a hybrid equalization structure. The FFE provides precursor ISI correction capability while the DFFE adds multi-tap postcursor correction with decision-directed operation. This combination achieves both precursor and postcursor ISI correction without the noise amplification problems of pure FFE.
Data Source
AI summary
A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.