Multi-Technology Module LVS Testing via Netlist Comparison
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Solution Overview
Problem
Existing layout versus schematic (LVS) test programs face significant challenges in verifying the consistency of multi-technology electronic devices, as they are technology-dependent and struggle with detecting package shorts in complex devices with millions of components.
Innovation Solution
A method for testing the consistency between a schematic and physical implementation of an electronic circuit, which involves generating and comparing netlists, determining package shorts by examining the connection network of conductive segments, and using an interface module to convert technology-dependent artwork into a common format for netlist generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional LVS test programs are used for multi-technology devices, then technology-specific verification can be performed, but the system cannot handle devices with multiple different technologies and becomes unreliable
Solution Approach 1:
The patent introduces an intermediary module that converts technology-specific artwork formats into a common intermediate representation. This mediator enables different technology formats (semiconductor, PCB, etc.) to be processed uniformly, achieving both versatility across technologies and reliability in LVS testing through standardized processing
2Manufacturing precision
If complete netlist generation and comparison is performed for all conductive segments, then comprehensive verification is achieved, but computational workload becomes excessive for devices with millions of components
Solution Approach 1:
The patent extracts and identifies package shorts as a specific subset of potential errors that can be detected independently through targeted analysis of connection networks. By taking out this specific verification task from the complete LVS process, the system achieves comprehensive verification of critical errors without the computational burden of analyzing all conductive segments
Solution Approach 2:
The verification process is segmented into distinct phases: package short detection through connection network analysis, and complete LVS verification. This segmentation allows the system to perform targeted verification of critical errors efficiently, while maintaining the option for comprehensive verification when needed
3Measurement precision
If package shorts are detected by examining all conductive segments, then complete coverage is achieved, but computational complexity increases significantly
Solution Approach 1:
The patent extracts the package short detection function as a separate, optimized process that examines only the connection networks relevant to package pins. This extraction maintains detection accuracy by focusing on the specific pathways where package shorts can occur, while reducing computational complexity by avoiding analysis of all conductive segments in the device
Data Source
AI summary
A method for operating a data processing system that causes the data processing system to test the consistency between a schematic description of an electronic circuit and a physical implementation of that circuit includes a master device having a plurality of component devices connected by a network of conductors is disclosed. Each of the component devices has a plurality of package pins that connect the component device to the network of conductors. Information specifying a schematic netlist generated from the schematic description and specifying a layout description of the physical implementation is received by the data processing system. The layout description specifies the network of conductors. The data processing system determines any package shorts in the component devices and generates a layout netlist from the layout description. The layout netlist is compared with the schematic netlist.