Multithread Controller Cache Tag Supervision
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Solution Overview
Problem
Current multithread processor systems face inefficiencies in thread switching and exclusive access control due to cache latency and increased pin count, leading to performance degradation and unnecessary thread switching, particularly in large-scale SMP systems.
Innovation Solution
A control method and apparatus that utilize cache line addresses and WAY-IDs for thread processing units to manage exclusive access and thread switching without increasing chip size or power consumption, by comparing and updating supervising address information to prevent unnecessary thread switching and cache misses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical address supervision is implemented for exclusive access control, then access control reliability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts only the necessary address components (WAY-ID and cache line address) from the complete physical address for supervision purposes. This selective extraction reduces the supervision burden while maintaining exclusive access control reliability, as these components are sufficient to identify cache blocks without requiring full physical address comparison.
Solution Approach 2:
The patent makes the cache tag memory serve multiple functions: it not only stores cache data identifiers for normal cache operations but also performs exclusive access control supervision. By utilizing the existing cache tag structure for dual purposes, the system avoids adding separate supervision hardware, thereby reducing device complexity while maintaining reliability.
2Reliability
If cache supervision mechanisms are added to prevent cache misses, then processing reliability is improved, but power consumption and chip size increase
Solution Approach 1:
The patent merges the exclusive access control supervision function with the existing cache tag memory operations. The same hardware structure that manages cache data identification is utilized for access supervision, eliminating the need for separate supervision memory and reducing overall power consumption while improving cache access reliability.
Solution Approach 2:
The cache system performs self-supervision by utilizing its own tag memory structure for exclusive access control. The cache memory serves itself by incorporating supervision capabilities within its existing framework, avoiding additional power-consuming supervision hardware while maintaining reliability.
3Speed
If thread switching is performed frequently to handle cache misses, then processing efficiency is improved, but productivity decreases due to unnecessary context switching
Solution Approach 1:
The patent implements feedback mechanisms that monitor cache access patterns and supervision results to make intelligent thread switching decisions. By analyzing cache hit/miss patterns and supervision outcomes, the system can distinguish between necessary thread switching (for actual cache misses) and unnecessary switching, thereby maintaining processing speed while improving effective productivity.
Solution Approach 2:
The patent performs preliminary supervision checks using WAY-ID and cache line address comparison before actual cache access occurs. This preliminary action identifies potential cache misses in advance, allowing the system to prepare appropriate responses and avoid unnecessary thread switching, thus improving both speed and productivity.
Data Source
AI summary
A multithread control apparatus and control method to switch a plurality of threads in a multithread processor, which includes a plurality of thread processors to execute the plurality of threads, by executing a synchronization lock control by considering release of exclusive access right to a relevant thread processor when a particular block in caches is updated with another processor or another thread processor during execution of a certain thread processor.