Multithread Processor Dynamic Schedule Switching for Interrupt Handling
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Solution Overview
Problem
Multi-thread processors face challenges in allocating sufficient processing power for high-priority interrupt processing, such as communication control in real-time systems, leading to potential system errors due to inadequate resource distribution.
Innovation Solution
A multi-thread processor with a thread scheduler that can switch between two schedules, allowing for swift selection of an optimal thread schedule based on the processor's state, reducing overhead during state changes and ensuring adequate resource allocation for interrupt processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-thread processor uses fixed time-sharing schedule for thread execution, then processing power is distributed among multiple threads, but interrupt processing with high priority cannot obtain sufficient processing power
Solution Approach 1:
The patent implements dynamic schedule switching that allows the processor to transition between a first schedule (time-sharing mode) and a second schedule (interrupt-priority mode). When an interrupt occurs, the processor switches to the second schedule that prioritizes interrupt processing, and returns to the first schedule after interrupt completion. This dynamic adaptation resolves the contradiction by making the scheduling policy flexible rather than fixed.
Solution Approach 2:
The patent changes the scheduling parameters (thread selection criteria, time allocation) based on the processor's operational state. In normal operation, the processor uses parameters configured for time-sharing among multiple threads. Upon interrupt occurrence, the parameters are changed to prioritize interrupt handling threads, ensuring sufficient processing power is allocated to high-priority interrupts while maintaining fair time-sharing during normal operation.
2Reliability
If the processor switches thread schedule in response to interrupt occurrence, then interrupt processing priority is improved, but processing time is lost due to schedule switching overhead
Solution Approach 1:
The patent prepares both the first schedule and the second schedule in advance, with the second schedule pre-configured for interrupt processing. When an interrupt occurs, the processor can immediately switch to the pre-prepared second schedule without performing complex real-time calculations or configurations, thereby minimizing the time loss associated with schedule switching.
Solution Approach 2:
The patent creates a copy of the scheduling mechanism (second schedule) that is specifically tailored for interrupt processing. This copy maintains the essential thread scheduling functionality but is optimized for interrupt scenarios, allowing rapid switching without duplicating the entire processor architecture or requiring extensive reconfiguration of existing structures.
3Adaptability or versatility
If the processor switches thread schedule by rewriting schedule register, then schedule change is achieved, but processing time is lost due to register rewriting operations
Solution Approach 1:
The patent pre-configures both the first schedule and the second schedule in schedule registers before switching is needed. The second schedule is prepared in advance with all necessary thread priority and allocation parameters, so that when an interrupt occurs, the processor only needs to load the pre-computed second schedule values into the schedule register rather than calculating them in real-time, significantly reducing the register rewriting time.
Data Source
AI summary
A multi-thread processor includes a plurality of hardware threads each of which generates an independent instruction flow, a first thread scheduler that continuously outputs a thread selection signal uniformly in a first period of a cycle of the first schedule pattern in accordance with a first schedule pattern or continuously outputs the thread selection signal uniformly in a second period of a cycle of the second schedule pattern in accordance with a second schedule pattern, the thread selection signal designating a hardware thread to be executed in a next execution cycle from among the plurality of hardware threads, a first selector that selects one of the plurality of hardware threads according to the thread selection signal and outputs an instruction generated by the selected hardware thread from among the plurality of hardware threads, and an execution pipeline that executes an instruction output from the first selector.