Multithread Processor Issue Scheduling for Priority Response
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Solution Overview
Problem
Existing processor technologies face challenges in maintaining processing efficiency and guaranteeing response time while strictly adhering to software-specified priorities, especially in control systems where throughput often suffers to ensure execution time, and there is a lack of capability to supply remaining resources to other electronic control units.
Innovation Solution
The processor incorporates an issue instruction multiplexer that uses issue information to determine the optimal operating cycle for instruction issuance, allowing high-priority instructions to be issued immediately and low-priority instructions to be scheduled in empty slots, enabling hot standby states and efficient resource allocation without saving or restoring processor state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware adjusts priority to increase processing efficiency, then throughput is improved, but execution time is prolonged compared to single-threaded processing
Solution Approach 1:
The processor performs preliminary actions by pre-decrementing the issue counter when an instruction is issued, and pre-calculating the issue timing for subsequent instructions. This allows the processor to maintain strict priority ordering while efficiently utilizing multiple threads, resolving the contradiction between processing efficiency and execution time by preparing timing information in advance rather than adjusting priorities dynamically.
Solution Approach 2:
The invention introduces dynamic timing adjustment through the issue counter mechanism. Instead of static priority assignment, the system dynamically determines when each thread can issue instructions based on the issue counter state. This dynamic approach allows the processor to maintain throughput benefits of multithreading while guaranteeing execution time by controlling the rhythm of instruction issuance rather than merely adjusting priority levels.
2Productivity
If throughput is emphasized in control systems, then processing efficiency is improved, but response time cannot be guaranteed
Solution Approach 1:
The processor implements a feedback mechanism through the issue counter that continuously monitors and adjusts the timing of instruction issuance. When a thread's turn arrives based on the counter, it receives priority access to execution resources. This feedback loop ensures that response time is guaranteed for critical threads while maintaining high throughput for all threads, resolving the contradiction between throughput and response time reliability.
3Stability of the object's composition
If strict priority maintenance is enforced, then software-specified ordering is preserved, but instruction issuance becomes restricted even when higher priority threads are ready
Solution Approach 1:
The processor performs preliminary action by pre-decrementing the issue counter at the moment of instruction issuance. This ensures that when a thread's priority turn arrives, the counter has already been updated to reflect the correct timing. This preliminary update allows strict priority maintenance while maximizing instruction issuance capability, as the counter naturally prevents premature or premature-like issuances without restricting valid high-priority threads.
Data Source
AI summary
To guarantee response time while strictly maintaining the priority specified by software, a processor (1) which is a multithread processor having a thread multiplexer (10), and an issue information buffer (ISINF). An instruction code, and issue information (isid) for instructions issued at and after the next operating cycle which is added to the instruction code, are supplied to the thread multiplexer. The issue information is valid from the second and subsequent instruction flows, and is saved temporarily in an issue information buffer. This issue information is for example the position of an operating cycle which can issue a high priority instruction, i.e., information showing a slot. The thread multiplexer issues a low priority instruction at another operating cycle at which a high priority instruction is not issued according to the issue information.