Multithreaded Circuit Placement Scheduling Using Connectivity and Utilization Dependencies
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Solution Overview
Problem
Conventional integrated circuit (IC) placement techniques face limitations in scalability and processing time as they rely on static connectivity dependencies, unable to efficiently handle larger circuit designs due to limited multithreading capabilities.
Innovation Solution
The implementation of a multithreaded scheduling technique that incorporates both connectivity and utilization dependencies during the placement phase, allowing for dynamic relocation of circuit elements and increased processing threads, thereby enhancing the placement quality and reducing runtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional placement techniques use static connectivity dependencies, then the placement process is simple to implement, but the scalability and processing time deteriorate as circuit designs grow larger
Solution Approach 1:
The patent segments the placement process into multiple independent threads that can execute concurrently. Each thread handles a subset of circuit elements or bins, allowing parallel processing. The scheduler divides the work into manageable units that can be distributed across multiple threads, improving productivity without creating a single complex monolithic scheduler.
Solution Approach 2:
The patent introduces dynamic scheduling where the order of processing circuit elements is determined by connectivity and utilization dependencies that can change during the placement process. The scheduler dynamically adjusts the processing order based on current bin utilization and connectivity requirements, allowing the system to adapt to varying circuit designs and placement states.
2Productivity
If conventional placers are limited to four processing threads, then the device complexity remains manageable, but the productivity and scalability are restricted for larger circuit designs
Solution Approach 1:
The patent creates a universal scheduling framework that can accommodate any number of threads (four, eight, or more) within the same architectural paradigm. The scheduler is designed to be thread-agnostic, using a unified approach to manage connectivity and utilization dependencies regardless of the number of concurrent threads, thereby achieving high productivity without proportionally increasing complexity.
Solution Approach 2:
The patent adds a new dimension to the scheduling problem by introducing utilization dependency as an additional constraint dimension alongside connectivity dependency. This allows the scheduler to make more informed decisions about thread assignment and processing order, effectively managing increased parallelism by adding another layer of optimization criteria rather than simply increasing thread count.
3Manufacturing precision
If the placement process does not account for utilization dependencies, then the scheduling is simpler, but the placement quality deteriorates for larger circuit designs
Solution Approach 1:
The patent performs preliminary calculations of connectivity and utilization dependencies during the scheduling phase before actual relocation operations begin. By pre-computing these dependency metrics and using them to determine processing order, the system prepares the placement strategy in advance, improving placement quality without adding complexity during the actual relocation execution.
Solution Approach 2:
The patent implements feedback mechanisms where the scheduler continuously monitors bin utilization and connectivity changes during the placement process. This feedback information is used to dynamically adjust the processing order and thread assignments, creating an adaptive system that improves placement quality by responding to real-time conditions while managing complexity through automated feedback loops.
Data Source
AI summary
Placing a circuit design may include partitioning circuit elements of the circuit design into circuit element sets and grouping bins of an integrated circuit into bin sets. The bins include circuit elements of the circuit design from an initial placement. Placing a circuit design also may include determining a dependency connectivity metric for the circuit elements and, using a processor, selectively relocating circuit elements concurrently, for a plurality of iterations, using a cost metric for relocating the circuit elements and using an order of processing the circuit elements determined from the bin sets, the circuit element sets, and the dependency connectivity metrics.