Multithreaded Instruction Dispatch Using Queue Tokens to Prevent Livelock

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Solution Overview

Problem

Simultaneous multithreading processors face inefficiencies and livelock issues due to resource congestion and conflicts between threads, leading to reduced performance and unfair thread scheduling.

Innovation Solution

An instruction dispatching method for multithreaded processors that determines thread instruction requests for congestion and conflict with execution waiting queues, using token availability and priority algorithms to select and dispatch instructions efficiently and fairly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple threads simultaneously dispatch instructions to execution waiting queues, then instruction-level parallelism increases, but resource congestion and conflict occur leading to livelock

Engineering Contradiction:
Improveinstruction dispatching throughputVSAvoidthread scheduling stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies preliminary action by checking token availability in execution waiting queues before dispatching instructions. The front-end determines whether tokens are available in advance, and only dispatches instructions when tokens are sufficient, preventing congestion and livelock conditions before they occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback mechanisms where the back-end execution units provide information about token consumption and queue status back to the front-end dispatching unit. This feedback loop enables dynamic adjustment of instruction dispatching based on current queue conditions, preventing resource exhaustion and livelock.

Inventive Principle:
Principle #23Feedback

2Speed

If instructions are dispatched without checking token availability, then dispatching speed increases, but resource exhaustion and livelock occur

Engineering Contradiction:
Improveinstruction dispatching speedVSAvoideffective instruction execution
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The patent performs preliminary checks of token availability in execution waiting queues before dispatching instructions. The front-end dispatching unit queries the back-end to determine if sufficient tokens exist, and only proceeds with dispatching when the condition is met, ensuring effective execution without waste.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies preliminary anti-action by preventing instruction dispatch when token availability indicates potential congestion or livelock conditions. The system proactively blocks dispatching before resource exhaustion occurs, counteracting the harmful effect of premature queue saturation.

Inventive Principle:
Principle #9Preliminary anti-action

3Ease of operation

If thread scheduling is performed without conflict detection, then scheduling simplicity is maintained, but unfairness and performance degradation occur

Engineering Contradiction:
Improvescheduling complexityVSAvoidthread execution efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent implements feedback-based conflict detection where the dispatching unit monitors token consumption patterns and queue status across multiple threads. When conflicts are detected through this feedback mechanism, the system adjusts scheduling decisions to ensure fair resource allocation and maintain high execution efficiency.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12608210B2Instruction dispatching method and apparatus for multithreaded processor, and storage medium
Publication Date: 2026.04.21 HYGON INFORMATION TECH CO LTD
  • US12608210B2 patent drawing
  • US12608210B2 patent drawing
  • US12608210B2 patent drawing

AI summary

An instruction dispatching method and apparatus for a multithreaded processor, and a storage medium are provided. The instruction dispatching method includes: receiving a plurality of thread instruction dispatching requests sent by a plurality of decoded instruction queues of the multithreaded processor, respectively, each of the plurality of thread instruction dispatching requests including a plurality of instructions needing to be transmitted to execution waiting queues of corresponding types, respectively; determining whether the plurality of thread instruction dispatching requests have congestion and conflict with respect to a plurality of execution waiting queues of the multithreaded processor; and selecting and responding to one thread instruction dispatching request from the plurality of thread instruction dispatching requests based on the determining.