Multi-threaded DMA Arbitration for Flexible Data Transfer
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Solution Overview
Problem
Traditional Direct Memory Access (DMA) circuits are inflexible due to their point-to-point communication links, limiting their performance in certain applications and failing to meet the needs of modern systems that require more complex data transfer capabilities.
Innovation Solution
The development of multi-threaded DMA circuits with multipoint-to-multipoint communication capabilities, allowing for four threads on the read port and two threads on the write port, along with advanced arbitration and scheduling mechanisms, to enhance flexibility and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional point-to-point DMA channels are used, then the system structure is simple, but the system flexibility and performance are limited
Solution Approach 1:
The patent implements a universal DMA architecture where a single DMA controller can handle multiple communication modes (point-to-point, point-to-multipoint, multipoint-to-point, multipoint-to-multipoint) through configurable channels. Each channel can be dynamically configured to operate in different modes, allowing the same hardware structure to adapt to various application requirements without needing separate dedicated circuits for each mode.
Solution Approach 2:
The DMA system employs dynamic channel configuration where channels can be programmatically set to different operational modes based on real-time requirements. The arbitration mechanism dynamically selects which channel operates in which mode, and the system can reconfigure channel assignments during runtime to optimize performance for different data transfer scenarios.
2Adaptability or versatility
If multiple channels share ports with arbitration, then system flexibility improves, but device complexity increases
Solution Approach 1:
The DMA controller is segmented into multiple independent channels, each capable of operating autonomously in different modes. The arbitration logic is segmented to handle each channel independently, allowing parallel processing of multiple data streams. This segmentation enables complex multi-channel sharing without requiring a monolithic control structure.
Solution Approach 2:
The patent introduces an arbitration mechanism that acts as an intermediary between multiple channels and shared ports. This mediator intelligently allocates port access rights based on priority levels and current system state, managing the complexity of channel sharing while maintaining efficient data transfer. The arbitration logic mediates conflicts between channels without requiring complex direct channel-to-channel coordination.
Data Source
AI summary
A direct memory access (DMA) circuit (200) includes a read port (202) and a write port (204). The DMA circuit (200) is a multithreaded initiator with “m” threads on the read port (202) and “n” threads on the write port (204). The DMA circuit (200) includes two decoupled read and write contexts and schedulers (302, 304) that provide for more efficient buffering and pipelining. The schedulers (302, 304) are mainly arbitrating between channels at a thread boundary. One thread is associated to one DMA service where a service can be a single or burst transaction. The multithreaded DMA transfer allows for concurrent channel transfers.