Multi-Threaded DRAM Unit Cell Layout for High-Bandwidth Low-Power Access
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Solution Overview
Problem
Current DRAM systems face challenges in achieving high random access bandwidth, reduced access latency, low power consumption, increased memory capacity, and improved refresh schemes, particularly in complex applications like machine learning, where existing HBM architectures struggle with power penalties and limited random address access rates.
Innovation Solution
An integrated circuit chip design featuring an array of independently accessible DRAM unit cells with single-ended sense amplifiers, multiplexer circuits, and through silicon vias, allowing for efficient layout and data transfer, reducing power consumption, and increasing memory capacity and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional HBM architectures are used to increase data bandwidth, then data bandwidth is improved, but power consumption increases significantly
Solution Approach 1:
The memory system is divided into multiple independently accessible DRAM unit cells, each capable of handling separate transactions. This segmentation allows parallel access to multiple memory locations, increasing bandwidth without requiring proportionally higher power consumption per transaction.
Solution Approach 2:
The DRAM unit cells are designed to handle multiple types of access operations (read, write, refresh) and support various addressing modes through a unified architecture. This multi-functionality allows the same hardware to serve multiple purposes efficiently, improving bandwidth utilization without additional power overhead.
2Quantity of substance
If the number of DRAM unit cells is increased to improve memory capacity, then memory capacity increases, but access latency increases
Solution Approach 1:
By organizing memory into multiple independent unit cells that can be accessed in parallel, the system can service multiple memory requests simultaneously. This reduces the effective access latency even as total memory capacity increases, since not all memory locations need to be accessed sequentially.
Solution Approach 2:
The patent employs three-dimensional stacked memory architecture with through-silicon vias, adding a vertical dimension to memory organization. This allows multiple layers of DRAM unit cells to be accessed independently, increasing capacity without proportionally increasing access time, as different layers can be accessed in parallel.
3Productivity
If wide-interface architecture is used to achieve high-speed operation, then data bandwidth is improved, but device complexity increases
Solution Approach 1:
Instead of using a single wide interface, the system segments the interface into multiple narrower channels that can operate in parallel. Each channel connects to a separate DRAM unit cell, simplifying the interface logic while achieving equivalent or superior bandwidth through parallelism.
Solution Approach 2:
The patent transitions from a two-dimensional planar interface architecture to a three-dimensional stacked architecture with vertical through-silicon via connections. This adds a vertical dimension to data paths, allowing multiple independent interfaces to coexist without increasing lateral complexity, thereby achieving high bandwidth with manageable device complexity.
Data Source
AI summary
An integrated circuit chip comprising an array of unit cells, each including a plurality of memory strips, each including a plurality of independently accessible DRAM sub-arrays arranged in a row and a corresponding pair of primary single-ended sense amplifier circuits coupled to each of the DRAM sub-arrays. The DRAM sub-arrays of the plurality of memory strips are further arranged in a plurality of columns. Each unit cell further includes a plurality of global bit line sets, each coupled to the primary single-ended sense amplifier circuits of a corresponding column of DRAM sub-arrays, a multiplexer circuit coupled to each of the global bit line sets, wherein the multiplexer circuit selectively couples one of the global bit line sets to a set of global input/output lines, a secondary sense amplifier circuit coupled to the set of global input/output lines, and plural through silicon vias coupled to the secondary sense amplifier circuit.