Multi-threaded FIFO Memory with Speculative Access
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Solution Overview
Problem
Conventional generators fail to produce synthesizable code for a shared FIFO memory that can efficiently store data for multiple threads in multi-threaded processing systems, leading to increased die area usage and inefficiencies.
Innovation Solution
A synthesizable code generator produces code for a single FIFO memory that can store data for multiple threads, incorporating a sender interface with speculative write capability and a receiver interface with speculative read capability, allowing independent access and data management for each thread.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate FIFO memories are used for each thread, then independent data access for each thread is achieved, but die area increases
Solution Approach 1:
The patent merges multiple thread-specific FIFO memories into a single shared FIFO memory structure. The generator produces synthesizable code that implements a unified memory array where data from multiple threads is stored together, eliminating the need for separate physical FIFOs for each thread while maintaining logical independence through thread identification fields in the data structure.
Solution Approach 2:
The shared FIFO memory is designed to serve multiple threads simultaneously through a universal interface. The memory structure includes thread identification fields and control logic that allows any thread to access its designated data within the shared memory space, making the single FIFO memory multi-functional for supporting N different execution threads.
2Area of stationary object
If a single shared FIFO memory is used for multiple threads, then die area is reduced, but independent access control for each thread becomes complex
Solution Approach 1:
The patent segments the shared FIFO memory by incorporating thread identification fields within each stored data entry. Each data element is tagged with its originating thread ID, allowing the control logic to route read/write operations to the correct logical channel without requiring complex physical segmentation or separate memory structures for each thread.
Solution Approach 2:
The patent introduces thread identification fields and associated control logic as intermediaries between the shared memory structure and multiple threads. These intermediaries manage the mapping between thread IDs and memory locations, simplifying access control by providing a standardized interface that handles thread-specific operations within the unified memory framework.
3Ease of manufacture
If conventional generators are used, then simple FIFO code is produced, but multi-threaded shared FIFO capability is not achieved
Solution Approach 1:
The patent implements dynamic thread management within the FIFO memory through programmable control logic. The generator produces code that allows runtime configuration of thread priorities, data rates, and access patterns, enabling the shared FIFO to adapt to varying multi-threaded workloads while maintaining efficient resource utilization through dynamic allocation and arbitration mechanisms.
Data Source
AI summary
Systems and methods for generating synthesizable code representing first-in first-out (FIFO) memories may be used to produce FIFO memories for multi-threaded processing. A single FIFO memory is shared between the threads to conserve die area, however each thread may be executed independently, as if each thread has a dedicated FIFO memory. A synthesizable code generator produces synthesizable code for a sender interface, storage, receiver interface, and other features that are specified by a programmer. The other features may reduce power consumption or improve timing. The code generator is used to efficiently produce different variations of FIFO memories.