Multitier Memory Bitline Structure for Low-Resistance Interconnects
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Solution Overview
Problem
Existing technologies face challenges in forming multitier arrangements of integrated devices, particularly in coupling sense/access lines with memory devices in upper tiers while also connecting them with components in lower tiers through interconnects, requiring structures and methods that enhance conductivity and reliability across different materials and configurations.
Innovation Solution
The implementation of multitier architectures where sense/access lines, such as bitlines, are composed of different materials over memory cells and conductive interconnects, with regions directly contacting the interconnects having lower resistance than those contacting memory cell electrodes, enabling enhanced signal transfer and improved speed and reliability by using conductive materials like tungsten and tantalum nitride for interconnects and chalcogenide materials for memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sense/access lines are formed to extend through upper tier memory devices to connect with lower tier components, then inter-tier electrical coupling is achieved, but signal transfer speed and reliability deteriorate due to increased resistance across multiple materials and interfaces
Solution Approach 1:
The patent applies local quality by using different material compositions for different regions of the sense/access lines. Specifically, the bitline uses tungsten in regions over interconnects (where low resistance is critical for signal transfer speed) and tantalum nitride in regions over memory cells (where appropriate conductivity for memory operation is needed). This regional material differentiation resolves the contradiction by optimizing each segment for its specific functional requirements.
Solution Approach 2:
The patent employs composite materials by forming bitlines with multiple material layers including tungsten, tantalum nitride, and other conductive materials. The bitline is constructed as a composite structure where different materials are combined to achieve both low resistance for fast signal transfer and appropriate electrical characteristics for memory cell operation, thereby resolving the speed-reliability contradiction.
2Reliability
If different materials are used for sense/access line regions over interconnects versus memory cells, then conductivity is optimized for each region, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the bitline formation process into distinct stages: first forming a tungsten layer across the entire structure, then selectively removing tungsten from regions over memory cells, and finally forming tantalum nitride in those specific regions. This segmented approach allows different materials to be placed in different regions while using sequential, standardized fabrication processes, thereby managing manufacturing complexity.
Solution Approach 2:
The patent uses preliminary action by first forming the tungsten layer across the entire substrate before selectively removing it from specific regions. This preliminary formation simplifies the overall process by using a single initial deposition step, followed by selective removal and targeted replacement, rather than attempting to deposit different materials simultaneously or in complex sequences.
3Productivity
If multitier arrangements are formed with interconnects extending through upper tiers, then integration density is improved, but difficulty in forming reliable electrical connections increases
Solution Approach 1:
The patent applies the intermediary principle by using tungsten as a mediator material that is first formed across the entire structure, then selectively removed from regions where direct contact with memory cells is needed. The tungsten serves as an intermediate layer that facilitates the subsequent formation of tantalum nitride in precise locations, simplifying the overall connection formation process while maintaining high integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient electrical coupling between tiers, improving signal transfer speed and reliability by optimizing the conductivity of bitlines over interconnects and memory cells, addressing the limitations of previous technologies in multitier device integration.
Implementation Method 1
sense/access lines (e.g., bitlines) which are coupled with memory devices of the upper tier, and which are also coupled with components of the lower tier through interconnects that extend through the upper tier
Implementation Method 2
regions directly contacting the interconnects having lower resistance than those contacting memory cell electrodes, enabling enhanced signal transfer and improved speed and reliability
Data Source
AI summary
Some embodiments include an arrangement having a memory tier with memory cells on opposing sides of a coupling region. First sense/access lines are under the memory cells, and are electrically connected with the memory cells. A conductive interconnect is within the coupling region. A second sense/access line extends across the memory cells, and across the conductive interconnect. The second sense/access line has a first region having a second conductive material over a first conductive material, and has a second region having only the second conductive material. The first region is over the memory cells, and is electrically connected with the memory cells. The second region is over the conductive interconnect and is electrically coupled with the conductive interconnect. An additional tier is under the memory tier, and includes CMOS circuitry coupled with the conductive interconnect. Some embodiments include methods of forming multitier arrangements.