Multi-Tier Block Sub-Block Programming with NAND Pre-Charging

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Solution Overview

Problem

In semiconductor memory devices, particularly in 3D memory structures, there are challenges related to block yield, data allocation efficiency, and garbage collection as the size of the block increases, along with issues in managing defective word lines and optimizing programming operations.

Innovation Solution

The implementation of a multi-tier block structure where memory cells are arranged in sub-blocks, allowing for individual sub-block erasure, marking defective sub-blocks as bad while using the rest, and optimizing pre-charging of NAND string channels during programming operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the size of the block increases to improve storage capacity, then storage capacity is improved, but block yield and data allocation efficiency deteriorate

Engineering Contradiction:
Improvestorage capacityVSAvoiddata allocation efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The patent divides a large memory block into multiple sub-blocks, allowing independent management and operation of each sub-block. This segmentation enables more flexible data allocation and improves efficiency by allowing operations on smaller units rather than the entire large block, thereby resolving the contradiction between storage capacity and data allocation efficiency.

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If the size of the block increases to improve storage capacity, then storage capacity is improved, but garbage collection becomes more difficult

Engineering Contradiction:
Improvestorage capacityVSAvoidgarbage collection
Core Design Contradiction:
Quantity of substanceVSEase of operation

Solution Approach 1:

By segmenting the large block into sub-blocks, the patent enables more manageable garbage collection operations. Each sub-block can be independently managed, making it easier to identify and collect garbage data without having to process the entire large block at once, thus improving the ease of garbage collection while maintaining high storage capacity.

Inventive Principle:
Principle #1Segmentation

3Quantity of substance

If the size of the block increases to improve storage capacity, then storage capacity is improved, but management of defective word lines becomes more complex

Engineering Contradiction:
Improvestorage capacityVSAvoidmanagement complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the large block into smaller sub-blocks, which simplifies the management of defective word lines. When a word line is defective, only the affected sub-block needs to be marked or managed, rather than the entire large block. This segmentation reduces the complexity of tracking and managing defects while maintaining the overall storage capacity.

Inventive Principle:
Principle #1Segmentation

4Productivity

If individual sub-block erasure is implemented to improve data allocation efficiency, then data allocation speed is improved, but device complexity increases

Engineering Contradiction:
Improvedata allocation speedVSAvoidcontrol complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements sub-block level control by dividing the block into manageable sub-blocks with independent control mechanisms. This segmentation enables faster data allocation by operating on smaller units, while the modular control structure keeps the increased complexity organized and manageable through systematic control of each sub-block independently.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11664075B2Sub-block programming mode with multi-tier block
Publication Date: 2023.05.30 SANDISK TECHNOLOGIES LLC
  • US11664075B2 patent drawing
  • US11664075B2 patent drawing
  • US11664075B2 patent drawing

AI summary

Apparatuses and techniques are described for programming a multi-tier block in which sub-blocks are arranged in respective tiers. When a program operation involves the source-side sub-block, the NAND strings are pre-charged from the source line. When a program operation involves the drain-side sub-block, the NAND strings are pre-charged from the bit line. When a program operation involves an interior sub-block, the NAND strings can be pre-charged from the bit line if all sub-blocks on the drain side of the interior sub-block are erased, or from the source line if all sub-blocks on the source side of the interior sub-block are erased. A table can be provided which identifies free blocks, free sub-blocks and a corresponding program order. If such a table is not available, the sub-blocks can be read to determine whether they are programmed.