Multi-Tile GPU Data Access With Page Sharing and Prefetching

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Solution Overview

Problem

Current graphics processing systems face inefficiencies in data access and sharing, particularly in multi-tile graphics processor architectures where geometry data is distributed across tiles, leading to performance bottlenecks.

Innovation Solution

The implementation of page sharing across GPU sockets, page faulting avoidance, and software-assisted hardware prefetching to improve data access and sharing efficiency in graphics processing units.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If geometry data is distributed across tiles in multi-tile graphics processor architecture, then processing parallelism is improved, but data access latency increases due to scattered data locations

Engineering Contradiction:

Improveprocessing parallelismVSAvoiddata access latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent implements a prefetching mechanism that proactively loads geometry data from memory into cache before it is actually needed by the processing units. The prefetcher monitors access patterns and anticipates future data needs, retrieving data in advance to eliminate wait times during processing operations.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces a cache memory system as an intermediary layer between the distributed tile processors and the main memory. This cache acts as a buffer that stores frequently accessed geometry data, allowing processors to retrieve data quickly from local cache rather than accessing distant memory locations directly.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If multiple processing units access data in memory simultaneously, then processing throughput is improved, but data access conflicts and bottlenecks increase

Engineering Contradiction:

Improveprocessing throughputVSAvoiddata access conflict management

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the cache memory into multiple independent sets or ways, allowing different processing units to access different cache segments simultaneously. This segmentation reduces contention by providing multiple parallel access paths, enabling concurrent operations without conflicts.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent implements a multi-dimensional cache address mapping scheme that distributes data across different cache dimensions (sets, ways, tags). By adding dimensional organization to the cache structure, the system provides multiple access paths and reduces bottlenecks through spatial and temporal distribution of data access.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS12204487B2Graphics processor data access and sharing

Publication Date: 2025.01.21 INTEL CORP

AI summary

Embodiments are generally directed to graphics processor data access and sharing. An embodiment of an apparatus includes a circuit element to produce a result in processing of an application; a load-store unit to receive the result and generate pre-fetch information for a cache utilizing the result; and a prefetch generator to produce prefetch addresses based at least in part on the pre-fetch information; wherein the load-store unit is to receive software assistance for prefetching, and wherein generation of the pre-fetch information is based at least in part on the software assistance.