Multivalent Oxide Cap for Low-Temperature Gate Stacks
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Solution Overview
Problem
High mobility channel materials in semiconductor devices, such as high Ge content SiGe, carbon nanotubes, and III-V materials, are not compatible with high temperature annealing processes used in traditional work function schemes for gate stacks with multiple work functions, limiting the ability to achieve both high and low threshold voltages on the same substrate.
Innovation Solution
The use of multivalent oxide caps, like CeOx, on high-k dielectric layers that modify oxygen chemical potential through oxidation and reduction reactions, allowing for the creation of gate stacks with both high and low threshold voltages without requiring high temperature annealing, by depositing these oxide layers directly on the high-k dielectric layers and selectively patterning them to achieve different threshold voltages for nFET and pFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional high temperature annealing processes are used to create gate stacks with multiple work functions, then both high and low threshold voltages can be achieved, but high mobility channel materials such as high Ge content SiGe, carbon nanotubes, and III-V materials cannot be used due to temperature incompatibility
Solution Approach 1:
The patent changes the processing temperature parameter from high temperature annealing to low temperature deposition and formation processes. By using atomic layer deposition (ALD) and chemical vapor deposition (CVD) at lower temperatures, the process becomes compatible with high mobility channel materials that cannot withstand high temperature annealing, thereby resolving the contradiction between achieving multiple work functions and protecting temperature-sensitive materials
Solution Approach 2:
The patent performs preliminary actions by depositing the high-k dielectric layer, interfacial layer, and oxide cap layer before final gate electrode formation. This preliminary deposition sequence allows the high-k dielectric and channel material to be formed and stabilized at low temperatures before any subsequent processing, enabling the use of temperature-sensitive high mobility channel materials while still allowing for later work function adjustment through selective oxide removal
2Temperature
If multivalent oxide caps are deposited directly on high-k dielectric layers at low temperatures, then high mobility channel materials can be used, but the ability to achieve multiple work functions on the same substrate is limited
Solution Approach 1:
The patent applies local quality by selectively removing the oxide cap layer from specific transistor regions (nFET or pFET) while leaving it intact on other regions. This selective removal creates different local conditions: regions with oxide caps maintain one work function, while regions without oxide caps have a different work function. This enables multiple threshold voltages on the same substrate using low temperature processing, resolving the contradiction between low temperature compatibility and multiple work function capability
Solution Approach 2:
The patent segments the substrate into different transistor regions (nFET and pFET areas) and applies different treatments to each segment. By dividing the device into regions that will have different oxide cap configurations, the process enables multiple work functions to be achieved on the same substrate through low temperature processing, as each segment can be independently configured for its required threshold voltage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with multiple work function gate stacks that can withstand lower processing temperatures, allowing for both high and low threshold voltages to be achieved on the same substrate, improving device variability and compatibility with advanced channel materials.
Implementation Method 1
modify oxygen chemical potential through oxidation and reduction reactions
Implementation Method 2
modify oxygen chemical potential through oxidation and reduction reactions
Implementation Method 3
a high-k dielectric layer arranged on a channel region
Data Source
AI summary
A method of fabricating a semiconductor device includes providing a high-k dielectric layer arranged on a channel region including a first transistor area and a second transistor area. The method further includes depositing a multivalent oxide layer directly on the high-k dielectric layer of the first transistor area. The method includes depositing a first work function metal on the multivalent oxide layer of the first transistor area and directly on the high-k dielectric layer of the second transistor area.