Multi-Value FET Structure for Stable Ternary Logic Switching
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Solution Overview
Problem
Existing multi-threshold transistor techniques for ternary logic circuits require extra passive devices, such as resistors or voltage sources, leading to electrical hysteresis and non-full swing output issues, and are sensitive to doping and process fluctuations, affecting the stability of multi-value logic units.
Innovation Solution
A FET with a multi-value switching function is designed with an undoped channel and drain region, utilizing metal blocks as inducer gates and a gate-oxide inducer layer to achieve electrostatic doping, eliminating the need for chemical doping and passive devices, and ensuring stability against doping and process fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multi-threshold transistor technique is used to construct ternary logic circuit, then ternary logic behavior can be realized, but extra off-chip resistor or voltage source is needed and more transistors are required
Solution Approach 1:
The invention extracts and eliminates the need for extra passive devices (resistors, voltage sources) by using the intrinsic properties of the transistor structure itself. The multi-threshold behavior is achieved through carefully engineered heterostructure layers with different bandgaps, allowing the transistor to naturally exhibit multiple threshold voltages without external passive components.
Solution Approach 2:
The transistor structure is designed to perform multiple functions: it provides both the switching functionality and the multi-threshold behavior through its heterostructure design. The different semiconductor layers serve dual purposes of forming the transistor channel and creating the multiple threshold voltage levels needed for ternary logic operations.
2Device complexity
If T-CMOS is used to construct multi-value logic unit, then extra passive device is not needed, but N-type T-CMOS should completely match P-type T-CMOS in current characteristics which is difficult to achieve due to doping fluctuations
Solution Approach 1:
The invention changes the fundamental parameter approach from relying on doping concentration to using material composition and layer thickness. By controlling the thickness of heterostructure layers and their bandgap energies, the threshold voltages are precisely tuned without depending on doping fluctuations, ensuring consistent matching between N-type and P-type devices.
Solution Approach 2:
The transistor uses composite semiconductor structures with different materials having different bandgaps. This composite approach allows precise control of electrical characteristics through material selection and layer design, replacing the traditional single-material doping approach that suffers from variability.
3Adaptability or versatility
If inter-band tunneling current is used as leakage current in T-CMOS, then third output level is formed, but the current is extremely likely to be affected by doping fluctuations of substrate and drain voltage
Solution Approach 1:
The invention substitutes the doping-based mechanism with a structural/physical mechanism. Instead of relying on doping-induced band bending that is sensitive to voltage fluctuations, the multiple thresholds are created by physical heterostructure barriers with different heights, making the system insensitive to electrical perturbations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The FET achieves stable ternary logic behavior without extra passive devices, reducing the influence of doping fluctuations and process limitations, and maintaining consistent current characteristics between N-type and P-type devices, enhancing the performance of multi-value logic units.
Implementation Method 1
the second metal block and the third metal block are used for generating a tunnel junction at a joint interface of the channel region and the drain region
Data Source
AI summary
A FET with a multi-value switching function comprises a source region, a channel region, a drain region, a gate dielectric layer, a substrate layer, a gate-oxide inducer layer, a metal layer and a spacer layer. The channel region is an undoped channel region, the drain region is an undoped drain region. The metal layer comprises first to third metal blocks which are arranged at intervals from left to right, the distance between the first metal block and the second metal block is 12 nm, the distance between the second metal block and the third metal block is 10 nm, the first metal block is a main control gate of the FET, the second metal block and the third metal block are two inducer gates of the FET, and the spacer layer is used for isolating the first metal block from the second metal block and the third metal block.