Multivalued Microprocessor Architecture for Pin-Limited Data Transfer
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Solution Overview
Problem
Current computers based on two-valued logic are reaching performance limits, with clock speed increases becoming difficult and multi-core approaches not significantly improving performance due to data transfer limitations, necessitating a shift to multivalued logic to enhance computing speed.
Innovation Solution
Designing and implementing multivalued logic circuits, including multivalued logic gates, memory cells, and flip-flops to create multivalued microprocessors that operate on four-valued logic, allowing each wire or CPU pin to have four states, thereby doubling data transfer capacity without increasing pins, and extending to higher n-value logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-core approach is used to improve performance, then processing capacity increases, but data transfer capacity remains limited due to pin count constraints
Solution Approach 1:
The patent changes the fundamental parameter of logic states from 2 to 4 (or higher n-values). Each CPU pin can represent 4 states instead of 2, effectively doubling the data transfer capacity per pin without increasing the physical pin count. This allows multi-core processors to communicate more efficiently with connected components.
Solution Approach 2:
The patent combines multiple logic states into a single physical pin. Instead of requiring separate pins for each binary state, multiple states (0, 1, 2, 3) are merged into one pin through multivalued logic encoding, increasing data throughput while maintaining the same physical interface.
2Speed
If clock speed is increased to improve performance, then computational speed increases, but physical and thermal limits are approached
Solution Approach 1:
The patent changes the logic system from 2-valued to n-valued (e.g., 4-valued) logic, which fundamentally alters how computational tasks are executed. This allows more information to be processed per clock cycle, potentially reducing the need for extreme clock speed increases and associated thermal challenges.
3Quantity of substance
If n-valued logic is implemented to increase data transfer capacity, then each pin carries more states, but circuit complexity increases
Solution Approach 1:
The patent segments the multivalued logic system into standardized building blocks: multivalued logic gates, memory cells, and flip-flops. Each component handles a specific function with n-valued logic, making the overall complex system manageable through modular design and standardized interfaces.
Solution Approach 2:
The patent creates universal multivalued logic components that can perform multiple functions. For example, multivalued logic gates can implement various logical operations, and memory cells can store multiple bits per cell, reducing the overall number of components needed while maintaining versatility.
Data Source
AI summary
A multivalued microprocessor including a multivalued processing module having a plurality of multivalued processing units constructed with multivalued logic gates. The microprocessor also includes a multivalued register file having a plurality of registers, wherein the registers are constructed with multivalued memory cells. The multivalued microprocessors utilizes two memory modules constructed with multivalued memory cells: one for storing solely instructions and one for storing solely data. A plurality of multivalued buses transmit multivalued data between the processing module, the register file, and the memory modules. A methodology for designing multivalued circuits that are constructed with multivalued logic gates and memory cells. The designs of multivalued memory cells, multivalued tristate buffers, and multivalued decoders using multivalued logic gates.