Multi-Vdd Compute-in-Memory Analog Processing
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Solution Overview
Problem
Conventional computer systems are inefficient for data-intensive applications like machine learning due to high power consumption and slow compute times caused by excessive data transfers between memory and processors, and existing compute-in-memory systems face challenges with power consumption and bandwidth limitations.
Innovation Solution
Implementing a multi-Vdd compute-in-memory device that eliminates the need for pulse-width or voltage amplitude modulation for weighted row access operations and using analog multipliers with capacitive charge sharing to reduce power consumption and increase bandwidth, allowing for direct computation within the memory array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional computer hardware is used to process large quantities of data in software, then data processing capability is achieved, but power consumption increases and compute time slows due to excessive data transfers between memory and processor
Solution Approach 1:
The patent merges memory storage and processing functions into a single integrated structure by implementing processing circuits directly within the memory device. This allows data to be processed in-place without transfer between separate memory and processor components, thereby improving data processing speed while reducing power consumption associated with data movement.
Solution Approach 2:
The patent introduces an analog processing circuit as an intermediary between digital memory cells and digital output. This analog circuit performs computations on data while it resides in memory, acting as a mediator that enables processing without full digital conversion and transfer, thus improving efficiency and reducing power consumption.
2Loss of energy
If compute-in-memory systems are implemented to reduce data transfer, then power consumption decreases and bandwidth increases, but the system requires complex circuitry for weighted row access operations
Solution Approach 1:
The patent extracts the processing function from traditional digital logic circuits and implements it using analog circuits within the memory device. This extraction allows weighted row access operations to be performed through analog voltage modulation rather than complex digital switching, reducing circuit complexity while maintaining the power consumption benefits of compute-in-memory.
Solution Approach 2:
The patent replaces digital switching mechanisms with analog voltage control for weighted row access. Instead of using complex digital logic to implement weighted access, the system uses analog voltage levels to directly represent weights, substituting mechanical/digital switching with continuous analog control, thereby reducing circuit complexity.
3Productivity
If analog processing circuits are used in memory devices to perform computations, then data transfer is minimized and processing efficiency improves, but bandwidth limitations arise from the analog circuitry
Solution Approach 1:
The patent implements dynamic voltage control in the analog processing circuit, allowing the system to adapt voltage levels based on computational requirements. This dynamic approach enables the analog circuit to operate at optimal speeds for different operations, improving bandwidth while maintaining processing efficiency through adaptive voltage scaling rather than fixed operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and increases bandwidth, enabling more efficient processing of large data sets, particularly in machine learning applications, by performing computations directly within the memory array and minimizing data transfer.
Implementation Method 1
capacitors coupled with conductive access lines of the multiple sub-arrays, the capacitors to share charge between themselves
Data Source
AI summary
Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.