Multivoltage Clock Synchronization via Edge Selection
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Solution Overview
Problem
Conventional level converter circuits in CMOS Analog-to-Digital Converters (ADCs) face significant distortion due to asymmetry in transition-dependent delay times, leading to misalignment of low-voltage and high-voltage clocks, which affects high-frequency operation and introduces sampling jitter.
Innovation Solution
A level converter circuit that selects the best edge from two complementary level converters to generate an optimized output clock, ensuring minimum delay and maintaining duty-cycle symmetry by utilizing the outputs where one has the minimum propagation delay in the high-to-low transition and the other in the low-to-high transition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional level converter circuit is used to transfer clock signals from low-voltage to high-voltage domain, then the clock signal can be transferred between voltage domains, but transition-dependent delay times cause duty cycle distortion and misalignment between LV and HV clocks
Solution Approach 1:
The patent divides the level converter into two separate converters: a first level converter for high-to-low transition and a second level converter for low-to-high transition. Each converter is optimized for its specific transition direction, allowing independent optimization of propagation delays for rising and falling edges, thereby eliminating duty cycle distortion while maintaining clock alignment between voltage domains
Solution Approach 2:
The patent applies different circuit topologies and transistor configurations to the first and second level converters tailored to their specific functions. The first converter uses structures optimized for high-to-low transition with weaker PMOS, while the second converter uses structures optimized for low-to-high transition, ensuring each achieves minimum propagation delay for its respective transition type
2Reliability
If delay is added to align low-voltage clocks with high-voltage clocks, then clock alignment is improved, but propagation delay of the level converter increases
Solution Approach 1:
By segmenting the level converter into two direction-specific converters, the patent eliminates the need for additional delay compensation. Each converter achieves minimum propagation delay for its transition direction through optimized circuit design, resulting in symmetric overall delay that maintains clock alignment without requiring extra delay elements
Solution Approach 2:
The patent optimizes circuit parameters including transistor widths, lengths, and strengths for each level converter based on its specific transition requirements. By adjusting these parameters locally in each converter, the patent achieves minimum propagation delay for both rising and falling edges while maintaining symmetry for proper clock alignment
Data Source
AI summary
A level converter circuit is disclosed. The level converter circuit includes a first level converter that generates a first output signal, and a second level converter that generates a second output signal. The level converter circuit further includes an edge selector coupled to the first level converter and the second level converter that selects a rising edge of either the first output signal or the second output signal, and selects a falling edge of either the first output signal or the second output signal to generate an optimized output signal.