Multi-Wire FEC Permutation for Burst-Error-Resilient Buses
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Solution Overview
Problem
In high-speed chip-to-chip communication systems, conventional methods for transmitting data over multi-wire buses face challenges in minimizing communication errors and latency, especially when dealing with burst errors and sequential data transmission.
Innovation Solution
The proposed solution involves permuting the transmission order of FEC-encoded packets from multiple encoding streams, ensuring that sequential packets from each stream are not transmitted sequentially on the same sub-channel or simultaneously on another sub-channel, thereby optimizing burst error control and latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sequential packets from each stream are transmitted sequentially on the same sub-channel, then transmission simplicity is maintained, but burst error control and latency are worsened
Solution Approach 1:
The patent segments the transmission process by dividing packets from multiple encoding streams into separate transmission groups. Each group contains packets from different streams that are transmitted in a permuted order across sub-channels, rather than transmitting sequential packets from a single stream on the same sub-channel. This segmentation improves burst error control while managing complexity through structured organization.
Solution Approach 2:
The patent introduces a new dimension of transmission organization by implementing permutation across multiple dimensions: stream dimension, sub-channel dimension, and time dimension. Instead of simple sequential transmission, packets are reordered across these dimensions to distribute burst errors more effectively, transforming the transmission structure from one-dimensional to multi-dimensional organization.
2Loss of time
If conventional FEC encoding is used without permutation, then encoding simplicity is maintained, but error correction latency increases
Solution Approach 1:
The patent applies preliminary action by performing permutation of packet transmission order before the actual transmission and error correction processes. By pre-organizing packets in a permuted sequence that distributes potential burst errors, the system reduces the latency required for error correction, as the permutation structure is established in advance rather than requiring complex real-time processing during error correction.
3Productivity
If high-speed transmission is implemented over multi-wire buses, then bandwidth is improved, but communication errors increase
Solution Approach 1:
The patent changes the transmission parameter of packet ordering by implementing permutation across multiple encoding streams and sub-channels. This parameter change allows high-speed transmission over multi-wire buses to maintain improved bandwidth while reducing communication errors, as the permuted transmission pattern distributes and mitigates the impact of burst errors that occur at high speeds.
Data Source
AI summary
Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.