Multiword Memory ECC Layout for Single-Bit Correction
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Solution Overview
Problem
Traditional methods for generating error correction codes for bit errors in large memory arrays are inefficient, requiring excessive storage overhead and being non-scalable, especially for arrays with unknown dimensions, and are not easily feasible for real-time computation.
Innovation Solution
A system and method that generates an error correction code by computing checkbits and parities for each word in a memory array, using bitwise logical exclusive OR operations and parity calculations to form a cumulative parity bit, which reduces storage overhead and improves scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional error correction code is applied to each M-bit word individually, then single bit error correction and double bit error detection capability is achieved, but storage overhead becomes excessive requiring 114,688 checkbits for a 16,384-word array
Solution Approach 1:
The patent segments the error correction process into two levels: (1) individual word-level checkbits are computed for each M-bit word to provide local error correction capability, and (2) array-level checkbits are computed across all N words to provide global error detection and correction. This segmentation allows the system to achieve comprehensive error protection while reducing total checkbit requirements compared to applying full SEC-DED to every word independently.
Solution Approach 2:
The patent merges word-level error correction with array-level error detection by combining individual checkbits from multiple words into a unified error correction code structure. The array-level checkbits are generated by combining data from all N words, creating a hierarchical error correction system that efficiently utilizes checkbit resources while maintaining protection against both single and double bit errors across the entire array.
2Quantity of substance
If entire large array is considered as input to error correction code engine, then storage overhead for checkbits is minimized, but computation must be performed on all bits at once which is not feasible and not easily scalable
Solution Approach 1:
The patent divides the computation into manageable segments: first computing checkbits for individual words or small groups of words, then combining these results to generate array-level checkbits. This segmented approach breaks down the computationally intensive task of processing entire large arrays into smaller, feasible operations that can be performed incrementally, making the system scalable to arbitrary array sizes.
Solution Approach 2:
The patent performs preliminary computation of word-level checkbits for individual words before combining them to generate the final array-level error correction code. This preliminary action allows the system to prepare intermediate results that simplify the final computation step, making the overall process more efficient and scalable compared to computing everything simultaneously.
3Reliability
If traditional approach computes error correction code for each word separately, then error correction capability is maintained, but the system is not easily scalable to arbitrary arrays where N and M are not known ahead of time
Solution Approach 1:
The patent creates a universal error correction code structure that can adapt to arbitrary array dimensions N and M. The hierarchical approach with word-level and array-level checkbits provides a flexible framework that maintains error correction capability while being easily scalable to different array sizes and configurations, making it suitable for systems where dimensions are not known in advance.
Solution Approach 2:
The patent implements a dynamic error correction system where the number of checkbits and their organization can adapt to the actual array dimensions. The system computes the appropriate number of checkbits based on the actual N and M values at runtime, allowing it to scale dynamically to arbitrary array sizes without requiring fixed-dimensional design constraints.
Data Source
AI summary
An error correction code for an array of N words of M bits each may be generated by: (i) for each word of the N words, computing a respective set of checkbits for single-error correction of such word; (ii) computing a set of bit-position-related checkbits comprising a bitwise logical exclusive OR of all of the sets of checkbits for single-error correction of the N words; (iii) for each word of the N words, computing a respective parity for the respective set of checkbits and the word itself in order to form a vector of N parity bits; (iv) computing a set of word-related checkbits for single-error correction of the vector of N parity bits; and (v) computing a cumulative parity bit comprising a parity calculation of the set of bit-position-related checkbits, the set of word-related checkbits, and the vector of N parity bits.