Multi-Zoned Thin Film Transistor Fabrication via Self-Aligned Insulator Masking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for fabricating thin film transistors, particularly metal-oxide semiconductors, are limited by the resolution of optical lithography, resulting in large gate lengths that restrict electronic speed and frequency response, and introduce alignment errors and surface damage, making it difficult to achieve short channel lengths suitable for high-performance applications.
Innovation Solution
A method for fabricating bottom-gated metal-oxide thin film transistors with sub-micrometer channel lengths using self-aligned multiple conductivity zones, avoiding expensive lithography tools and enabling customization of channel conductivity, allowing for channel lengths as small as a few nanometers, and achieving deep sub-micrometer source-drain electrode spacing using optical lithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If optical lithography is used for fabricating thin film transistors, then large area electronics can be produced, but the gate length is limited to larger than 1 micrometer, restricting electronic speed and frequency response
Solution Approach 1:
The fabrication process is segmented into multiple self-aligned steps: first forming source and drain electrodes with insulator coverage, then selectively removing insulator to define the channel region. This segmentation allows the gate length to be defined by the insulator dimensions rather than lithography resolution, enabling sub-micrometer gate lengths while maintaining large area fabrication capability
Solution Approach 2:
The invention transitions from defining gate length in the lateral plane through lithography to defining it through vertical insulator layer thickness and selective removal. By using the vertical dimension (insulator layer height) to control the horizontal gate length, the process overcomes the lithography resolution limit while maintaining compatibility with large area substrates
2Speed
If advanced lithography techniques such as electron beams are used to achieve short gate lengths, then electronic speed improves, but device complexity and manufacturing cost increase significantly
Solution Approach 1:
The insulator layer serves multiple functions: it acts as a mask during source/drain electrode formation, defines the channel length through its thickness, and provides alignment reference for subsequent steps. This self-aligned approach eliminates the need for complex alignment procedures in advanced lithography, achieving short gate lengths with simpler optical lithography processes
Solution Approach 2:
The insulator layer is deposited and patterned before the source and drain electrodes are formed. This preliminary action establishes the channel length definition early in the process, allowing subsequent electrode formation to be simpler and more aligned, avoiding the need for complex real-time alignment in advanced lithography techniques
3Ease of manufacture
If uniform doping is used in short channel transistors, then manufacturing is simplified, but output conductance increases, reducing power gain
Solution Approach 1:
The doping process is applied locally to different regions of the channel: the first region near the source receives one doping level while the second region near the drain receives a different doping level. This local quality variation allows optimization of carrier concentration in each region to reduce output conductance and improve power gain, while the self-aligned structure keeps the process manageable
Data Source
AI summary
A method of fabricating a multi-zone, short gate length thin film transistor is provided. Gate metal and a plurality of layers are deposited on a substrate. The layers include a gate insulator, a first semiconductor, a second semiconductor, and source contact metal. An insulator is deposited on the plurality of layers partially overlapping the gate electrode and masking part of the plurality of layers. Portions of the source contact metal not masked by the insulator are removed and the first and second semiconductors are diffused with dopants via a plasma. Sidewalls of the insulator and source metal contact are covered with an insulating layer. Portions of the second semiconductor not masked are removed by etching for a length of time to create undercuts below the insulator and extending under the source contact metal. The undercuts are filled with an insulating material and an external metal contact layer is deposited.