Multi-Port Memory ABIST Using Functional Latch Shadowing

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Solution Overview

Problem

Existing Built-In Self Test (BIST) mechanisms for multi-port memory arrays require significant test-only hardware and are labor-intensive, making it difficult to test at functional speeds and potentially causing schedule slippage, especially when the memory is embedded in different chips or has slightly different implementations.

Innovation Solution

The solution involves using functional data latches from one port as shadow latches for another port during ABIST testing, minimizing the need for dedicated test-only hardware and allowing for functional speed testing of multi-ported memories.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated test-only shadow latches are added for each port, then scanning capability for ABIST is achieved, but chip area increases significantly

Engineering Contradiction:

ImproveABIST testing capabilityVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent makes functional latches serve dual purposes: they hold addresses during normal operation and function as shadow latches during ABIST scanning. This multi-functionality eliminates the need for dedicated test-only shadow latches, resolving the contradiction between achieving ABIST capability and minimizing chip area.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If AVP programs are developed late in the design process, then memory verification is achieved, but schedule slippage and labor costs increase

Engineering Contradiction:

Improvememory verificationVSAvoidschedule slippage

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements ABIST hardware that can operate independently of AVP programs, allowing memory array testing to be performed earlier in the design process without waiting for complex AVP development. This preliminary action capability reduces schedule slippage and labor costs while maintaining verification reliability.

Inventive Principle:

Principle #10Preliminary action

3Reliability

If traditional ABIST hardware is added for multi-port memory, then testing capability is improved, but the complexity of test hardware increases

Engineering Contradiction:

Improvetesting capabilityVSAvoidtest hardware complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the functional latch banks with the ABIST shadow latch functionality. By combining these previously separate components into a unified structure that operates in both functional and test modes, the patent reduces test hardware complexity while maintaining comprehensive testing capability for multi-port memory arrays.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS7506225B2Scanned memory testing of multi-port memory arrays

Publication Date: 2009.03.17 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A system for at-functional-clock-speed continuous scan array built-in self testing (ABIST) of multiport memory is disclosed. During ABIST testing, functional addressing latches from a first port are used as shadow latches for a second port's addressing latches. The arrangement reduces the amount of test-only hardware on a chip and reduces the need to write complex testing software. Higher level functions may be inserted between the shadow latches and the addressing latches to automatically provide functions such as inversions.