Bottom Electrode Via Placement for MUT Bonding Integrity
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Solution Overview
Problem
Existing micromachined ultrasonic transducer devices face challenges in achieving a smooth bonding interface due to surface planarization difficulties during the via formation process, which can negatively impact the integrity of the transducer membrane bonding.
Innovation Solution
The solution involves strategically locating the bottom electrode vias directly beneath the footprint of the transducer cavity, minimizing the impact of via planarization defects on the bonding interface. Additionally, a continuous thin film of via fill material is left on top of the vias to enhance device planarity during low-temperature bonding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are formed during the substrate processing, then electrical connection between bottom electrode layer and substrate is achieved, but surface planarization defects occur that negatively impact bonding interface integrity
Solution Approach 1:
The patent extracts the vias from the bonding interface region by positioning them directly below the transducer cavity footprint, separating the via formation process from the critical bonding area. This allows via planarization defects to be isolated away from the bonding interface, resolving the contradiction between achieving electrical connection and maintaining surface planarity for bonding.
Solution Approach 2:
The patent applies different quality requirements to different regions: the bonding interface region requires high surface planarity, while the via region below the cavity can tolerate planarization defects. This localized quality approach allows via formation without compromising bonding interface integrity.
2Manufacturing precision
If CMP process is used for planarization, then surface flatness is improved, but surface irregularities still remain that affect low-temperature bonding
Solution Approach 1:
The patent takes preliminary action by strategically positioning vias below the cavity footprint before the bonding process, preventing surface irregularities from affecting the bonding interface. This preemptive placement counteracts the potential harmful effects of CMP-induced irregularities on bonding integrity.
Solution Approach 2:
The patent converts the potential harm of via planarization defects into a benefit by positioning them in a location where they do not interfere with bonding. The defects are effectively hidden below the cavity, transforming a manufacturing challenge into a non-critical feature.
3Reliability
If vias are positioned outside the cavity footprint, then bonding interface is protected from via defects, but electrical connection path becomes longer
Solution Approach 1:
The patent resolves the path length issue by moving the via placement into the vertical dimension below the cavity footprint, rather than positioning them laterally outside the cavity. This dimensional repositioning maintains short electrical connection paths while protecting the bonding interface, as the vias are vertically displaced rather than laterally separated.
Data Source
AI summary
An ultrasound transducer device includes an electrode, a membrane separated from the electrode by a cavity between the membrane and the electrode, a patterned membrane support layer that defines a size and shape of the cavity and that is disposed between the electrode and the membrane, and vias that electrically connect the electrode to a substrate. The vias are disposed in the ultrasound transducer device such that less than 50% of the vias overlap with a support surface of the patterned membrane support layer, in a plan view.