MUTEX Arbiter Circuit for Metastability-Free Request Ordering
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Solution Overview
Problem
Existing arbiter circuits in electronic devices often enter a metastable state when multiple request signals are received simultaneously, leading to inconsistent granting of requests and potential deadlocks, especially when three or more requests arrive at the same time, which can disrupt normal operation and lead to system failure.
Innovation Solution
The proposed arbiter circuit employs a sequence identifier with MUTEX cells and feedback loops to identify the order of request signals, filter out glitches, and prevent forbidden states by momentarily disabling request signals when multiple requests arrive simultaneously, ensuring mutual exclusivity and preserving the original order of requests.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple request signals are received simultaneously by conventional arbiter circuits, then the circuit enters a metastable state, but this leads to inconsistent granting of requests and potential deadlocks
Solution Approach 1:
The arbiter circuit is divided into multiple independent 2-input MUTEX elements arranged in a mesh structure. Each MUTEX element handles a specific pair of request signals independently, allowing the system to process multiple simultaneous requests without entering a metastable state. The segmentation of the arbitration function across multiple simple elements resolves the contradiction by maintaining reliability through distributed decision-making while keeping individual elements simple.
Solution Approach 2:
The patent introduces intermediate grant signals and control logic that mediate between multiple simultaneous request signals. When conflicts are detected, the intermediary control mechanisms coordinate the granting of requests in a deterministic manner, preventing metastable states while maintaining consistent and fair request servicing. This intermediary layer resolves the contradiction by adding coordination complexity only where needed rather than throughout the entire circuit.
2Productivity
If mesh arbiter circuits are used to handle multiple requests, then request signals can be processed in parallel, but the circuit often needs to reject request signals and does not consistently grant requests in their original order
Solution Approach 1:
The arbiter circuit incorporates feedback mechanisms where grant signals are monitored and used to control subsequent arbitration decisions. When a request is granted, the feedback signal updates the state of MUTEX elements to prevent conflicting grants and maintain request order. This feedback loop ensures that parallel processing does not compromise request order preservation, resolving the contradiction between productivity and reliability.
Solution Approach 2:
The circuit performs preliminary detection of request conflicts before granting occurs. By anticipating potential order violations through advance detection logic, the arbiter can pre-coordinate grant timing to preserve request order even when processing requests in parallel. This preliminary action prevents order violations before they occur, maintaining reliability while enabling parallel processing for high productivity.
3Reliability
If ordered arbiters with windowing function are used to preserve request order, then the original order is maintained, but the 2nd and 3rd requests might be swapped if they occur at or around the same time with the 1st request
Solution Approach 1:
The arbiter circuit dynamically adjusts its arbitration behavior based on the timing relationships between incoming requests. When requests arrive within a critical time window, the circuit activates deterministic ordering logic; when requests are well-separated in time, it allows faster parallel processing. This dynamic adaptation resolves the contradiction by applying order-preserving mechanisms only when necessary, minimizing latency while maintaining reliability.
Solution Approach 2:
The patent combines multiple arbitration strategies (mesh MUTEX elements, windowing function, and conflict detection logic) into a composite arbiter structure. This composite approach leverages the strengths of each method: the mesh structure enables parallel processing, the windowing function preserves order for sequential requests, and conflict detection handles simultaneous arrivals. The combination resolves the contradiction by integrating multiple mechanisms that work together to maintain order without excessive latency.
4Loss of time
If low-latency ordered arbiter is used to maintain request order with low latency, then the original order is kept, but the circuit may lead to a deadlock when three requests arrive at the same time
Solution Approach 1:
The arbiter circuit implements partial deadlock prevention by detecting specific forbidden states (such as three simultaneous requests) and applying corrective action only in those cases. Rather than implementing complex deadlock prevention for all possible scenarios, the circuit uses simple detection logic for critical cases and allows fast processing for normal operations. This partial action resolves the contradiction by maintaining low latency for the majority of cases while preventing deadlocks in critical scenarios.
Solution Approach 2:
The circuit performs preliminary detection of forbidden states before deadlock can occur. By monitoring request patterns and identifying configurations that would lead to deadlock (such as three simultaneous requests), the arbiter can preemptively adjust its behavior to avoid the deadlock state. This preliminary anti-action resolves the contradiction by preventing deadlocks before they happen while maintaining low-latency operation for normal request patterns.
Data Source
AI summary
An arbiter for use with a plurality of request signals is presented. The arbiter includes a sequence identifier to identify an order between the plurality of request signals. The arbiter provides a plurality of output signals in which each output signal is associated with a request signal. When the request signals are provided in a sequential order the output signals are provided in the identified sequential order. When the request signals are provided substantially at the same time the output signals are provided in an arbitrary sequential order. A corresponding signal arbitration method and an electronic circuit comprising the arbiter are also presented.