Mutual-Interpolating DLL for 50% Duty Cycle Clock Generation
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Solution Overview
Problem
Conventional DLL circuits fail to guarantee high-quality clock signals with 50% duty cycles due to lack of physical architecture and circuit constraints, leading to degraded waveform and duty cycle issues, especially at high frequencies and with fabrication process variations.
Innovation Solution
A mutual-interpolating delay cell chain is introduced, where each delay cell receives and interpolates two or more delay clock signals from different cells, creating a set of simultaneous equations that ensure a 50% duty cycle for the generated clock signals through sub-loop feedback lines and an outer loop feedback circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DLL circuits are used for high-frequency clock generation, then clock frequency can be increased, but duty cycle accuracy deteriorates and waveform quality degrades
Solution Approach 1:
The patent implements a feedback mechanism where the output of each delay cell is fed back to subsequent delay cells through sub-loop feedback lines. This creates a system of simultaneous equations that constrains the duty cycle of each clock signal to 50%, ensuring duty cycle accuracy even at high frequencies where conventional DLL circuits would otherwise degrade waveform quality.
2Productivity
If conventional DLL circuits operate at high frequencies, then data processing rate increases, but tolerance to process and temperature variation decreases
Solution Approach 1:
The patent changes the fundamental parameters of the delay cell operation by introducing mutual interpolation through sub-loop feedback. This creates a system where the delay parameters are constrained by simultaneous equations, making the system's performance less sensitive to process and temperature variations. The 50% duty cycle constraint ensures consistent timing margins across varying operating conditions.
3Adaptability or versatility
If conventional DLL circuits generate multiphase clock signals, then system functionality increases, but waveform degradation occurs due to parasitic loading
Solution Approach 1:
The patent applies feedback by routing the output of each delay cell back to subsequent cells through sub-loop feedback lines. This feedback mechanism creates constraints that compensate for parasitic loading effects, maintaining waveform quality and 50% duty cycle accuracy even when generating multiple clock phases simultaneously.
4Device complexity
If conventional DLL circuits are used without additional constraints, then device complexity is reduced, but duty cycle control precision is insufficient
Solution Approach 1:
The patent introduces feedback through sub-loop feedback lines that connect delay cell outputs back to subsequent cells. This feedback structure automatically enforces duty cycle constraints without requiring additional complex control circuitry, achieving precise 50% duty cycle control while maintaining relatively simple device architecture.
Data Source
AI summary
A delay-locked loop (DLL) circuit with mutual-interpolating architecture that provides multiple-phase clock generation is presented. Each delay-cell in the DLL circuit delay chain is effectively an interpolator that combines two input clock signals: one input clock signal is received from the output clock of previous stage in the delay chain, and the other input clock signal is fed back from a following stage. Each delay cell supports the concurrent functions of delay and interpolation. The architecture imposes a set of N simultaneous equations, where N is the total number of delay clock signals, to control the clock waveforms. These simultaneous equations obtain a unique solution when the DLL enters a lock state, and the generated delay clock signals inherently have a clock duty cycle of 50%. The delay chain can be implemented using either odd or even number of delay cells.