Mux-D Scan Flip-Flop Topology Without Critical Path Scan Delay
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Solution Overview
Problem
Existing microprocessor designs face challenges in reducing silicon cost, improving time-to-market, and slowing process technology scaling while maintaining high frequency and performance, power, and leakage budgets. Additionally, the overhead of scan logic in flip-flops consumes significant area and delays frequency.
Innovation Solution
The introduction of a fast Mux-D scan flip-flop that bypasses the traditional input data scan multiplexer to the master keeper side path, removing delay overhead and maintaining compatibility with simple scan methodologies, thus achieving high performance similar to level sensitive scan designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Mux-D scan multiplexer is used in flip-flop, then scan testability is provided, but area overhead and delay increase significantly
Solution Approach 1:
The patent extracts the scan multiplexer function from the traditional flip-flop structure and implements it as a separate scan gadget connected to the slave keeper side. This separation removes the scan mux delay from the critical data path while preserving scan testability, thereby reducing area overhead and delay in the main functional path.
Solution Approach 2:
The patent moves the scan functionality to a different dimensional space by connecting it to the slave keeper side rather than the master side. This dimensional shift allows the scan path to operate independently from the critical data path, eliminating the trade-off between scan testability and performance.
2Reliability
If traditional Mux-D scan multiplexer is used in flip-flop, then scan testability is provided, but frequency performance is limited by scan logic delay
Solution Approach 1:
The scan multiplexer is extracted from the critical data path and placed on the slave keeper side, where it does not affect the timing of the main data path. This extraction allows the flip-flop to achieve high frequency performance while maintaining scan testability through the separate scan gadget.
Solution Approach 2:
The patent segments the flip-flop into distinct functional blocks: the main data path with master and slave latches, and the separate scan gadget with its own multiplexer. This segmentation isolates the scan logic delay from the critical data path delay, allowing independent optimization of both scan testability and frequency performance.
3Reliability
If scan logic is included in flip-flop, then testability is improved, but standard cell size increases by approximately 70%
Solution Approach 1:
The patent merges the scan functionality with the existing slave keeper circuitry by connecting the scan gadget to the slave keeper side. This merging allows the scan multiplexer to share resources with the keeper circuit, reducing the overall area overhead compared to a separate scan implementation.
Solution Approach 2:
The slave keeper side is designed to serve dual purposes: maintaining the hold function during normal operation and providing scan testability when activated. This multi-functionality reduces the need for dedicated scan logic, thereby reducing area overhead while preserving both performance and testability.
Data Source
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AI summary
A fast Mux-D scan flip-flop (400) is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop (400) combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.