MUX and DEMUX LC Transmission Lines for Parasitic Capacitance
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Solution Overview
Problem
High-speed multiplexor and demultiplexer circuits face bandwidth limitations due to parasitic capacitances of field effect transistors, which restrict their frequency range and performance without additional power or faster switching.
Innovation Solution
The solution involves splitting current paths in multiplexers and demultiplexers into multiple sections with inductors and switches, where parasitic capacitances are absorbed by LC transmission lines, allowing for increased bandwidth without additional power or faster switches, and optimizing inductor and capacitor values to minimize reflection and delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional FET-based switching is used in MUX/DEMUX circuits, then the circuit structure is simple, but the parasitic capacitances of the FETs limit the bandwidth
Solution Approach 1:
LC transmission lines are introduced as intermediary elements between the FET switches and the signal paths. These transmission lines act as mediators that transform the harmful effect of parasitic capacitances into useful impedance matching, thereby extending bandwidth without complicating the core switching structure
Solution Approach 2:
The inductance and capacitance values of the LC transmission lines are carefully optimized to transform the parasitic capacitance effect. By adjusting these parameters, the transmission lines present a matched impedance to the switches across a broader frequency range, effectively extending bandwidth while maintaining structural simplicity
2Speed
If additional power or faster switches are used to increase bandwidth, then bandwidth improves, but power consumption increases
Solution Approach 1:
The LC transmission lines are designed to automatically compensate for parasitic capacitance effects through their inherent reactive properties. This self-service mechanism eliminates the need for additional power-consuming active compensation circuits or higher-power switches, achieving bandwidth extension without increasing power consumption
3Speed
If LC transmission lines are added to absorb parasitic capacitances, then bandwidth increases, but device complexity increases
Solution Approach 1:
The bandwidth extension function is segmented into discrete LC transmission line sections inserted at specific points in the signal path. This segmentation allows the complexity to be distributed and managed locally rather than requiring a complete circuit redesign, making the complexity increase more manageable and targeted
4Speed
If inductors and capacitors are optimized to minimize reflection and delay, then bandwidth and matching improve, but manufacturing precision requirements increase
Solution Approach 1:
The design incorporates feedback mechanisms where the transmission line parameters are optimized based on measured or simulated performance data. This iterative feedback process allows for compensation of manufacturing variations and achieves optimal bandwidth and matching while accounting for practical manufacturing tolerances
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach nearly doubles the bandwidth and matching of multiplexers and demultiplexers, achieving significant performance enhancements without increasing power consumption or switching speed, with bandwidth improvements up to 2.3 times the original values.
Implementation Method 1
The first and second inductors are sized such that parasitic capacitances of the first and second switches are substantially absorbed by the input and output LC transmission lines
Implementation Method 2
The first inductor is part of an output LC transmission line of the sub-circuit; the second inductor is part of an input LC transmission line of the sub-circuit
Data Source
AI summary
A combinational circuit (e.g., multiplexer or demultiplexer) comprises a sub-circuit that comprises first and second current paths from an input of the combinational circuit to an output of the combinational circuit, such that substantially all input current at the input of the combinational circuit is conducted by the sub-circuit via the first and second current paths to the output of the combinational circuit. The first current path comprises a first inductor and a first switch; and the second current path comprises a second inductor and a second switch. The first inductor is part of an output LC transmission line of the sub-circuit; the second inductor is part of an input LC transmission line of the sub-circuit; and the first and second inductors are sized such that parasitic capacitances of the first and second switches are substantially absorbed by the input and output LC transmission lines.