MUX Gate Line Layout for Reliable Touch Display Sensing
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Solution Overview
Problem
Existing display devices face challenges in reducing signal distortion and wiring damage while enhancing touch performance reliability.
Innovation Solution
The display device incorporates a unique design of MUX gate lines that do not overlap each other in a plan view, with specific configurations and connections to MUX transistors, including first and second MUX gate line portions extending in different directions and being spaced apart, along with a contact member for electrical connection, to minimize signal interference and protect wirings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MUX gate lines are arranged to extend in multiple directions to connect MUX transistors, then the electrical connection and control capability are improved, but the risk of signal distortion and wiring damage increases due to overlapping and interference
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement where gate lines overlap to a three-dimensional stacked arrangement where gate lines are positioned at different heights (first gate line at first height, second gate line at second height). This vertical separation eliminates planar overlap while maintaining electrical connectivity through vertical conductors, thereby reducing signal interference and wiring damage risk while preserving control capability.
Solution Approach 2:
The patent implements a nested structure where the second MUX gate line is positioned within the vertical projection area of the first MUX gate line, but at a different height level. The gate lines are nested in the vertical dimension rather than overlapping in the planar dimension, allowing dense routing without signal interference. This nested arrangement optimizes space utilization while maintaining signal integrity.
2Device complexity
If MUX gate lines are positioned closer to MUX transistors to reduce wiring length, then the device complexity is reduced, but the risk of signal distortion and wiring damage increases
Solution Approach 1:
The patent uses vertical stacking to bring gate lines close to MUX transistors in the three-dimensional space without planar overlap. The first and second gate lines are positioned at different heights, allowing them to approach the transistors closely while maintaining sufficient spacing in the planar view. This reduces wiring length and device complexity while avoiding signal interference that would occur with planar proximity.
Data Source
AI summary
A display device includes: a display part including a base layer and a light emitting element on the base layer; a sensing part on the display part, and including a sensing electrode; a multiplexer electrically connected to the sensing electrode through a sensing line, and including multiplexer (MUX) transistors on a portion of the base layer; and MUX gate lines electrically connected to the MUX transistors.