Multiplexing Output Stage Impedance Tuning for ISI Jitter Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing data rate requirements, particularly for 100 Gbps and 112 Gbps, are hindered by large jitter noise induced by intersymbol interference (ISI) effects, which distort signals and reduce communication reliability.
Innovation Solution
A multiplexing circuit is proposed, incorporating a first type transistor and multiple second type transistors, along with an impedance circuit, to convert input signals into serial output signals, effectively minimizing ISI by optimizing impedance and reducing capacitance loading, thus enhancing bandwidth capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating data rate is increased to meet higher bandwidth requirements, then the data transmission speed is improved, but the jitter noise from intersymbol interference (ISI) effects increases
Solution Approach 1:
The patent changes the impedance parameter of the output stage by using a transistor-based impedance circuit instead of a conventional resistive output stage. This impedance transformation optimizes the signal transmission characteristics, reduces ISI effects, and minimizes jitter noise, thereby maintaining signal reliability at higher data rates.
Solution Approach 2:
The patent replaces the conventional resistive output stage with an active transistor-based circuit implementation. This substitution uses the transistor's inherent electrical characteristics (gate-drain capacitance and transconductance) to achieve the desired impedance transformation, eliminating the need for external passive components and reducing signal degradation.
2Reliability
If physical passive inductors are used to reduce ISI effects, then the signal reliability is improved, but the chip area is increased
Solution Approach 1:
The patent extracts and eliminates the need for physical passive inductor components from the circuit design. By using the transistor's intrinsic capacitance and transconductance properties, the invention achieves the same signal conditioning effect without requiring external inductive elements, thereby conserving chip area.
Solution Approach 2:
The patent uses the transistor's gate-drain capacitance to replicate the function of an inductor in reducing ISI effects. This capacitive coupling approach copies the beneficial effect of inductive peaking (enhancing high-frequency signal components) without requiring actual inductive components, thus maintaining signal reliability while minimizing area.
Data Source
AI summary
A multiplexing circuit including a first type transistor, a second type transistor and an impedance circuit; a gate terminal of the first type transistor is configured to receive a control signal and free from receiving a clock signal; the second type transistor is coupled to the first type transistor, wherein a gate terminal of the second type transistor is configured to receive the clock signal, and the first type transistor is different from the second type transistor; the impedance circuit is arranged to provide an impedance between the gate terminal of the first type transistor and the second type transistor, wherein the impedance circuit is free from connecting to the gate terminal of the second type transistor.