MUX Select Control for Phase-Shifted Write Precompensation
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Solution Overview
Problem
In high-speed storage devices with magnetic storage media, bandwidth limitations in the write data path lead to degradation of recorded data, and existing precompensation techniques struggle to align preamp control signals with incoming data, especially when dealing with phase shifts greater than one period of the data.
Innovation Solution
A precompensation circuit that includes rising and falling edge interpolator circuits, a multiplexer, and a control circuit to generate a select signal based on phase-shifted data signals, allowing for dynamic gain adjustment of the preamp to counteract bandwidth limitations and align control signals with the data, enabling correct transmission of precompensated signals with phase shifts greater than one period.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precompensation is applied to correct magnetic transition shift, then data integrity is improved, but device complexity increases due to additional circuit components
Solution Approach 1:
The patent combines the preamp control signal generation and data precompensation into a single integrated circuit. The multiplexer selectively outputs either phase-shifted data or preamp control signal based on timing requirements, merging two functions into one device to reduce overall system complexity while maintaining data integrity through precompensation
Solution Approach 2:
The circuit implements multi-functionality by using a single integrated structure that can output both phase-shifted data signals and preamp control signals. The multiplexer enables the circuit to serve multiple purposes: data precompensation and control signal generation, reducing the need for separate dedicated circuits for each function
2Reliability
If dynamic gain control is applied to counteract bandwidth limitations, then signal quality is improved, but device complexity increases due to additional control circuits
Solution Approach 1:
The patent merges the dynamic gain control function with the data precompensation circuitry. The same integrated circuit that performs data precompensation also generates the preamp control signal for dynamic gain adjustment, eliminating the need for a separate control circuit and reducing overall device complexity while maintaining signal quality
Solution Approach 2:
The circuit achieves multi-functionality by simultaneously performing data precompensation and generating preamp control signals for dynamic gain control. This universal approach allows one circuit to handle multiple signal processing tasks, reducing the total number of components needed while improving signal quality through adaptive gain adjustment
3Manufacturing precision
If phase shifting greater than one period is applied to align control signals, then signal alignment is improved, but existing precompensation techniques fail to operate correctly
Solution Approach 1:
The patent implements dynamic phase shifting capability that can accommodate phase shifts greater than one period. The circuit uses a phase shifter that can be dynamically adjusted to provide the required phase alignment, and a multiplexer that adapts its selection based on the phase shift amount, enabling correct operation with large phase shifts that would fail in static or limited-range systems
Data Source
AI summary
A precompensation circuit can include: a rising edge interpolator circuit configured to generate a phase shifted rising edge data signal; a falling edge interpolator circuit configured to generate a phase shifted falling edge data signal; a multiplexer circuit coupled with the rising edge interpolator circuit and with the falling edge interpolator circuit to multiplex the phase shifted rising edge data signal and the phase shifted falling edge data signal into an output data signal responsive to a select signal; and a control circuit coupled with the select input of the multiplexer circuit to control production of the output data signal, wherein the control circuit is further coupled with both the rising edge interpolator circuit and the falling edge interpolator circuit to change the select signal to the multiplexer circuit at times determined by both the phase shifted rising edge data signal and the phase shifted falling edge data signal.


