MUX-Shared Processing Unit Layout for Memory Bank Utilization

Solution Overview

Problem

Existing memory devices face inefficiencies due to underutilization of processing units (PUs) and excess die space usage, as traditional implementations require multiple PUs per bank, leading to MAC units being inactive during read latency periods.

Innovation Solution

Implementing a multiplexor (MUX) between data sense amplifiers and a processing unit (PU) to share a single PU across multiple banks, allowing continuous data provision to MAC units, reducing the number of required MAC units and other circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple processing units are implemented per bank, then data processing capacity is sufficient, but die space is excessively used and cost increases

Engineering Contradiction:

Improvedata processing capacityVSAvoiddie space

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

A single processing unit is designed to serve multiple memory banks through the multiplexor interface. The processing unit can selectively receive data from different banks via the multiplexor, allowing one processing unit to handle data processing for multiple banks sequentially, thereby reducing the total number of processing units needed and minimizing die space while maintaining adequate data processing capacity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the data paths from multiple banks into a single processing unit through the use of a multiplexor. Instead of having separate dedicated processing units for each bank, the data paths are merged and time-multiplexed to a shared processing unit, reducing the overall number of processing units and associated MAC units required.

Inventive Principle:

Principle #5Merging (Combining)

2Productivity

If traditional processing unit implementation is used, then data processing is performed, but MAC units remain inactive during read latency periods causing underutilization

Engineering Contradiction:

ImproveMAC unit utilizationVSAvoidread latency idle time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The multiplexor is configured to continuously provide data to the processing unit during the read latency period. While one bank's data is being read, the multiplexor can switch to provide data from another bank, ensuring that the processing unit and MAC units remain active and productive throughout the entire read latency period, eliminating idle time and improving continuous utilization.

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The multiplexor implements periodic switching between different bank data sources during the read latency period. This periodic action allows the processing unit to receive continuous streams of data from different banks in sequence, keeping MAC units actively processing data throughout what would otherwise be idle latency periods.

Inventive Principle:

Principle #19Periodic action

3Reliability

If multiple processing units are implemented, then data processing redundancy is provided, but power consumption increases

Engineering Contradiction:

Improvedata processing redundancyVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

A single processing unit is designed to serve multiple memory banks through the multiplexor interface. The processing unit can selectively receive data from different banks via the multiplexor, allowing one processing unit to handle data processing for multiple banks sequentially, thereby reducing the total number of processing units needed and minimizing die space while maintaining adequate data processing capacity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the data paths from multiple banks into a single processing unit through the use of a multiplexor. Instead of having separate dedicated processing units for each bank, the data paths are merged and time-multiplexed to a shared processing unit, reducing the overall number of processing units and associated MAC units required.

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20260024576A1Multiplexor placement for implementing a processing unit in memory

Publication Date: 2026.01.22 MICRON TECHNOLOGY INC

AI summary

A memory device can include a first error correction code (ECC) circuitry, a second ECC circuitry, and a multiplexor (MUX). The first ECC circuitry receive first data from a first bank. The second ECC circuitry can receive second data from a second bank. A MUX can receive the first data from the first ECC circuitry and the second data from the second ECC circuitry. The MUX can provide the first data in a first portion of a duration of time. The MUX can provide the second data in a second portion of the duration of time. A processing unit (PU) can perform a first plurality of multiplication operations utilizing the first data provided by the MUX during the first portion of the duration of time and a second plurality of multiplication operations utilizing the second data provided by the MUX during the second portion of the duration of time.