MV Gate Spacer Integration to Reduce GIDL Leakage
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Solution Overview
Problem
In the manufacturing of semiconductor integrated circuits, medium voltage (MV) devices experience significant gate-induced drain leakage (GIDL) due to the shared gate spacers with low voltage (LV) devices, which limits the improvement of GIDL through existing methods like lightly doped drain (LDD) adjustments, with a small process window.
Innovation Solution
A process integration method that involves forming additional spacers in the MV device region, using a different material than the initial spacer material, and performing specific etching steps to increase the thickness of the MV device spacers beyond the LV device spacer thickness, thereby reducing GIDL leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate spacers are made thin to meet SRAM pitch requirements, then integration level is improved, but gate induced drain leakage (GIDL) in MV devices increases
Solution Approach 1:
The patent applies local quality by forming a thicker spacer layer specifically in the MV device region while maintaining the original thin spacer thickness in the LV device region. This is achieved through selective etching processes that remove spacer material from LV regions while preserving and thickening spacers in MV regions, allowing each device type to have optimized spacer dimensions for its specific requirements.
2Object-generated harmful factors
If LDD adjustment is used to improve GIDL, then leakage is reduced, but process window remains very limited
Solution Approach 1:
The patent changes the physical parameter of spacer thickness rather than relying on LDD doping adjustments. By controlling the spacer thickness to be greater than a first threshold value in MV devices, the patent achieves better GIDL suppression with a larger process window. This parameter change from doping concentration to geometric dimension provides more flexibility in process optimization.
3Temperature
If thicker gate dielectric layer is used in MV devices, then operating voltage is achieved, but GIDL leakage increases due to shared gate spacers
Solution Approach 1:
The patent applies local quality by differentiating spacer dimensions between MV and LV device regions. MV devices with thicker gate dielectric layers (for higher operating voltages) are paired with thicker spacers, while LV devices use thinner spacers. This local differentiation ensures that high-voltage devices have adequate spacing to suppress GIDL, while low-voltage devices maintain compact dimensions for high integration.
Data Source
AI summary
The application discloses a process integration method for improving leakage in MV devices, comprising: step I: forming gate structures, step II: depositing a first spacer material layer, step III: forming an additional spacer material layer, step IV: forming a first mask layer to cover an MV device formation region and open an LV device formation region, step V: performing an isotropic first etching to remove the additional spacer material layer from the LV device formation region, step VI: performing an anisotropic second etching to form a first layer of spacers of the low voltage region, step VII: forming a second mask layer to open the MV device formation region and to cover the LV device formation region, step VIII: performing an anisotropic third etching to form a first layer of spacers of the medium voltage region and additional spacers, and step IX: depositing and etching a second spacer material layer.