Middle-Voltage Transistor Structure with Graded Doping Against Leakage
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Solution Overview
Problem
Current semiconductor technologies face issues with current leakage due to the etching of the gate dielectric layer during the fabrication process, especially as feature sizes shrink and integration increases.
Innovation Solution
A middle voltage transistor structure is designed with two lightly doping regions surrounding a source/drain doping region, featuring a silicide layer that covers and contacts the source/drain doping region, and a second lightly doping region with a specific dopant concentration to prevent current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate dielectric layer is removed during fabrication, then the transistor can be completed, but current leakage occurs
Solution Approach 1:
A silicide layer is introduced as an intermediary between the gate dielectric layer and the source/drain doping region. This silicide layer prevents direct contact and current leakage while allowing the gate dielectric to be removed for transistor completion. The silicide layer acts as a mediator that resolves the conflict between completing the transistor structure and preventing current leakage.
Solution Approach 2:
The harmful gate dielectric layer is selectively removed (etched) from areas where it causes current leakage, while the silicide layer remains to provide the necessary electrical isolation. This extraction of the problematic element (gate dielectric) while retaining the protective element (silicide layer) resolves the contradiction between completing the transistor and preventing leakage.
2Productivity
If feature size shrinks to increase integration, then more elements can be integrated, but current leakage increases
Solution Approach 1:
The silicide layer is selectively formed only in specific locations where current leakage is problematic, rather than uniformly across the entire device. This local application of the silicide layer provides targeted protection against current leakage while maintaining high integration density, allowing feature sizes to shrink without proportionally increasing leakage.
3Reliability
If dopant concentration is increased to prevent electron punch-through, then current leakage is reduced, but manufacturing complexity increases
Solution Approach 1:
The doping structure is segmented into multiple regions with different dopant concentrations: a first lightly-doped region, a second lightly-doped region with higher concentration, and a source/drain doping region with the highest concentration. This segmentation allows each region to be optimized for its specific function, preventing electron punch-through through the graded concentration profile while maintaining manufacturing feasibility through systematic multi-step doping processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively prevents current leakage by ensuring a controlled dopant concentration gradient, reducing electron punch-through and enhancing the reliability of semiconductor devices.
Implementation Method 1
the second lightly doping region includes a first edge; a source/drain doping region is embedded within the second lightly doping region... the second lightly doping region surrounds the source/drain doping region... a controlled dopant concentration gradient
Implementation Method 2
A silicide layer covers and contacts the source/drain doping region, wherein the silicide layer includes an end, and the end is disposed between the first edge and the second edge
Implementation Method 3
a first ion implantation process is performed by taking the mask layer as a first mask to implant dopants into the substrate at two sides of the mask layer to form two first lightly doping regions
Data Source
AI summary
A middle voltage transistor includes a gate formed on a substrate and a gate dielectric layer wider than the gate. First and second spacers are disposed on the gate dielectric layer, with the second spacer having a convex surface. An interface is located between the first and second spacers. A first lightly doped region is formed under the gate, enclosing a second lightly doped region, which in turn encloses a source/drain doped region. A silicide layer covers the source/drain region, with its end located between the convex surface and the interface.