Multi-Value Digital Counter Readout Circuit for High Density Imaging
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Solution Overview
Problem
Conventional readout integrated circuits (ROICs) for digital imaging systems face limitations in pixel density due to the requirement for bulky in-pixel binary digital counters, which restrict the dynamic range and sensitivity, especially in high-demand applications like thermal infrared sensing and degraded visual environments.
Innovation Solution
The implementation of multi-value digital counters (MVDCs) within the ROIC, which use integration capacitors and comparators to convert signal charges into discrete, well-defined voltage levels, eliminating the need for binary counters and enabling higher pixel density and dynamic range without increasing component count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If in-pixel binary digital counters are used for digitization, then dynamic range is improved, but pixel density is limited due to bulky component requirements
Solution Approach 1:
The patent changes the base parameter of the digital counter from binary (base-2) to multi-value (base-N where N>2). This parameter change allows the counter to represent the same dynamic range with fewer discrete states, thereby reducing the number of required flip-flops and enabling higher pixel density while maintaining improved dynamic range performance
2Measurement precision
If conventional ADC circuits are implemented in-pixel, then sensitivity and dynamic range are improved, but device area increases limiting pixel density
Solution Approach 1:
The patent changes the fundamental operating parameter of the counter from binary to multi-value logic. This allows the in-pixel ADC to achieve high sensitivity and dynamic range with significantly fewer digital elements, directly reducing the area occupied per pixel and enabling higher pixel density
3Measurement precision
If binary digital counters are used for in-pixel digitization, then measurement accuracy is improved, but component count and circuit area increase
Solution Approach 1:
The patent changes the base parameter of the counter from 2 to N (where N>2), allowing each counter element to represent N distinct states instead of 2. This parameter change reduces the total number of flip-flops required to achieve the same measurement accuracy, thereby reducing component count and circuit area while maintaining measurement precision
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances pixel density and dynamic range while reducing power consumption and component complexity, allowing for faster image processing and higher sensitivity in digital imaging systems.
Implementation Method 1
each of the FPA elements or 'pixels' develops an analog output 'signal charge' that is proportional to the intensity of the light that is impinging on it
Implementation Method 2
the comparator monitors the charge of the integration capacitor and issues an output pulse spike that resets the integration capacitor each time the integrated charge reaches a specified threshold value
Data Source
AI summary
A high density, high speed ROIC uses in-pixel integration capacitors and comparators to convert each pixel charge to a train of pulse spikes which increment a capacitor to successive, discrete charge values that represent a digital, non-binary count value of an in-pixel multi-value digital counter (MVDC). The MVDC can include a plurality of stages whereby comparators limit the maximum count of each stage and increment subsequent stages. The maximum count can be a power of two for subsequent direct ADC conversion to binary. The count values and the residual integration capacitor charge can be read out by ramping the comparator reference inputs and measuring the comparator output timings, effectively forming partially in-pixel single-slope ADC's. The comparators can include temporary internal positive feedback to maintain consistency of the spike pulses to better than 10%.