Single MVL Clock Network for Multi-Phase Timing and Lower Power
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Solution Overview
Problem
Multi-phase clock distribution systems in high-performance digital integrated circuits require significant resources for area and power due to multiple independent clock networks, complicating synchronization and increasing power dissipation.
Innovation Solution
A single global clock distribution network for Multiple-Valued Logic (MVL) signals, utilizing modified level-sensitive latches and a binary-encoded clock signal, which can be implemented using commercially available FPGA devices or standard cell libraries, reducing the need for multiple clock distribution networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple independent clock distribution networks are used for multi-phase clocking, then high performance and timing closure are achieved, but area utilization and power dissipation increase significantly
Solution Approach 1:
The patent merges multiple independent clock distribution networks into a single shared clock distribution network. Instead of providing separate clock networks for each phase, the invention uses one network to distribute clock signals to multiple phases, thereby reducing area utilization while maintaining the ability to support multi-phase operation for high performance.
Solution Approach 2:
The single clock distribution network is designed to serve multiple functions by distributing clock signals to multiple phases. This universal network replaces the need for dedicated clock networks for each phase, allowing the same infrastructure to support high-performance multi-phase clocking across different circuit domains.
2Reliability
If multiple independent clock distribution networks are used for multi-phase clocking, then timing constraints within each phase are relaxed, but power dissipation increases due to multiple networks
Solution Approach 1:
The patent combines multiple power-consuming clock distribution networks into a single network, directly reducing power dissipation. The merged network maintains the ability to provide phase-specific clock signals with relaxed timing constraints, ensuring timing closure is achieved without the energy cost of multiple separate networks.
3Productivity
If multiple independent clock distribution networks are used, then each phase can operate concurrently, but synchronization among clock phases becomes complex
Solution Approach 1:
The patent merges the clock distribution function into a single network that inherently manages synchronization. By providing a unified distribution path, the network simplifies the synchronization of multiple clock phases while still enabling concurrent operation of different phases to maintain high throughput.
4Area of stationary object
If a single global clock distribution network is used, then area and power are reduced, but maintaining multiple clock phases becomes more difficult
Solution Approach 1:
The single clock distribution network is designed with universal functionality to support multiple clock phases. It can adaptively distribute appropriate clock signals to different circuit domains, maintaining multi-phase operation capability while using a unified network infrastructure, thus preserving adaptability without requiring multiple dedicated networks.
Data Source
AI summary
A multi-valued logic (MVL) circuit includes a MVL clock generator that generates a MVL clock signal having three or more ith MVL levels, a single MVL clock signal distribution network connected to the MVL clock generator, and three or more ith MVL selection circuits connected to the single MVL clock signal distribution network where i=0 to N and N>=3. Each ith MVL selection circuit corresponds to a specified ith MVL level. The ith MVL selection circuit outputs an ith binary clock signal having: (a) a first logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the first logic level, (b) a second logic level whenever the MVL clock signal is equal to the ith MVL level and the ith data input receives the second logic level, and (c) a previous logic level of the ith binary clock signal whenever the MVL clock signal is not equal to the ith MVL level.